A high magnetic coupling, low loss, stacked balun in digital 65nm CMOS

Akhtar, S.; Taylor, Richard; Litmanen, P.

doi:10.1109/rfic.2009.5135592

Cited by 5 publications

(2 citation statements)

References 2 publications

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“…The input signal is amplified in the voltage domain by the LNA and transformed into a differential signal by the passive balun. To save the chip area, a stacked single-to-differential balun architecture is adopted [30]. As shown in Fig.…”

Section: A Receiver Front-end Designmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a Bluetooth low-energy (BLE) transceiver (TRX) achieving ultra-low-power operation for Internet-of-Things (IoT) applications. The proposed TRX utilizes a wide-bandwidth low-power fractional-N digital phase-locked loop (DPLL) as a central component to perform multiple roles: a direct frequency modulator for the transmitter (TX), an analogto-digital converter (ADC) for the receiver (RX), a local oscillator for RX, and a frequency and phase synchronizer for the RX. The DPLL-based single-path downconversion method is adapted to halve the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. A DPLL-based ADC with a digital-to-analog converter feedback greatly improves the ADC dynamic range, which improves the RX sensitivity and interference tolerance. By maximally reducing the required radio frequency and analog front-end components in RX, an RX power consumption of 2.3 mW is achieved with a −94 dBm sensitivity. The RX also satisfied all interference requirements with a certain margin. A 5.0-mW TX is achieved when delivering an output power of 0 dBm with a frequency-shift keying error of only 1.89%.

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Section: A Receiver Front-end Designmentioning

confidence: 99%

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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“…2. The transformer is implemented horizontally with stacked layers of metal [5], so the area is similar to a load inductor. The transformer has a turns ratio of 5:3, which provides current gain.…”

Section: A Low Noise Amplifier Design and Transformermentioning

confidence: 99%

A 28mW WCDMA/GSM/GPRS/EDGE transformer-based receiver in 45nm CMOS

Srinivasan

Pennisi

Rentala

et al. 2010

2010 IEEE Radio Frequency Integrated Circuits Symposium

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A transformer-based receiver designed in 45nm CMOS that meets WCDMA, GSM, GPRS, and EDGE system requirements is presented. The receiver requires no interstage SAW filters and consumes 20mA from 1.4V. The use of a transformer at the LNA output helps achieve high linearity by lowering the voltage swing while simultaneously providing current gain. The analog back end is implemented with two cascaded gain stages and a 2 nd order ΣΔ ADC. The receiver has a gain of 60dB, noise figure of 3.0dB and an IIP2 of >+50dBm on both I+Q channels. The die area is 1.35mm 2 for 4 bands.

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