A high density datapath compiler mixing random logic with optimized blocks

Abstract

This paper presents a new datapath compiler providing high transistor densities. Mixing random logic with optimized blocks in the same bit-sliced structure is possible thanks to a dedicated datapath library. Automatic placement is perfornied according to the structural input description. Minimizrd cost functions are total wire length and track density. Track assignment, dealing with virtual tuminals, uses a divide and conquer approach to perform ejicient over-cell routing. In order to provide processindependence, a symbolic layout approach is used. This tool has been successjitlly used to design several high per-,formiice datapaths.

Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs

“…The user-defined modules are then placed as whole units and not merged with the remainder of the circuit. The methods described in [Cai90] and [Ben93] are representative for many similar approaches. In these algorithms, primitive (AND, OR, INV, MUX) as well as more complex modules (ADD, REG, SHIFT) are generated according to specified operand and result widths and pin arrangement.…”

“…The module generator component Paramog ( [Sad95], [Dit95], Figure 1) of SDI is implemented similarly to classical examples ( [Shu89], [Ben93]). Requests are parametrized by data types, bit widths, and area limits, and Paramog offers a selection of possible layouts realizing the specified function.…”

Structured design implementation

“…The module generator component Paramog ( [Sad95], [Dit95], Figure 1) of SDI is implemented similarly to classical examples ( [Shu89], [Ben93]). Requests are parametrized by data types, bit widths, and area limits, and Paramog offers a selection of possible layouts realizing the specified function.…”

Module compaction in FPGA-based regular datapaths

“…The application of generator programs to create their constituent modules has a long history in VLSI design ( [2], [6], [10], [13], [14], and many others). With growing FPGA die sizes, such datapath architectures are also implementable on FPGAs.…”