Module compaction in FPGA-based regular datapaths

Abstract

When relying on module generators to implement regular datapaths on FPGAs, the coarse granularity of FPGA cells can lead to area and delay inefficiencies. We present a method to alleviate these problems by compacting adjacent modules using structure extraction, local logic synthesis, and cell replacement. The regular datapath structure is exploited and preserved, achieving faster layouts after shorter tool run-times.

Synthesizing datapath circuits for FPGAs with emphasis on area minimization

“…Previous studies, [4] [7] [8] [9] [12] [13] [16], have shown that the logic density of FPGAs can be substantially increased by exploiting regularity at the placement, routing, and architecture levels. However, there are no extensive studies focusing on the effects of datapath synthesis on FPGA area.…”

“…However, there are no extensive studies focusing on the effects of datapath synthesis on FPGA area. Existing datapath synthesis techniques can be roughly classified into four categories: regularity preserving logic transformations [10] [11], hard boundary hierarchical synthesis (synthesis that performs optimizations strictly within user-defined module boundaries), template mapping [5] [6] [14] [15], and module compaction [8] [9]. Among these four synthesis techniques, only regularity preserving logic transformations do not incur significant area overhead [10].…”

“…A module compaction algorithm was first proposed by Koch in [8] and [9]. The algorithm consists of two basic steps.…”

“…Then, each merged module is synthesized using regular flat synthesis techniques. Area results on only two circuits are published in [8] and [9]. One circuit has 712 4-LUTs and the other has 112 4-LUTs (post datapath-synthesis area).…”