A high breakdown voltage IC with lateral power device based on SODI structure

The fabrication cost of bonded silicon on insulator (SOI) wafers for customized power devices is high owing to the high temperature required and the very long fabrication process involving both thermal oxidation and bonding. In addition, SOI wafers are contaminated with metallic impurities during the formation of the buried oxide (BOX) layer and the bonding of a silicon layer on the BOX layer. Therefore, we propose an alternative SOI wafer fabrication method combining BOX layer deposition and surface activated bonding at room temperature in a vacuum without any voids. There is also no fixed charge in the deposited BOX layer, and the breakdown voltage of this layer is 11–12 MV cm−1, the same as that for a thermal oxide layer.

Section: Introductionmentioning

confidence: 99%

SOI wafer fabricated with extremely thick deposited BOX layer using a surface activated bonding technique at room temperature

Koga

Kurita

2019

“…[1][2][3][4][5] The self-isolation technique is more cost effective than the junction isolation [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] and dielectric isolation techniques. [23][24][25][26][27][28][29][30] This is because it uses a lessexpensive silicon wafer that is uniformly doped, and it does not need special process steps such as deep diffusion layer and trench formations for the isolation process.…”

Section: Device Conceptmentioning

confidence: 99%

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Yamaji

Jonishi

Sumida

et al. 2015

A new 800 V-class lateral high-voltage n-channel MOS (HVNMOS) structure with a markedly reduced parasitic capacitance (C oss ) has been developed for integration in a high-voltage gate driver IC. In our new HVNMOS, a 40% C oss reduction from that of a conventional HVNMOS can be achieved by using two n-type drift regions divided by a p-type diffusion layer. We have confirmed that a 12% shorter I/O propagation delay time can be achieved by using the new HVNMOS of the high-voltage IC (HVIC) test chip. In this paper, the design concept of the developed HVNMOS is presented with the simulation and experimental results.

“…5) Akiyama et al reported that the higher BV of 1050 V was achieved in his lateral diode fabricated in silicon-on-double-insulator (SODI) structure, which was formed by backside silicon etching of SOI wafer followed by dielectric layer deposition and metal electrode formation. 6) Endo et al reported that his lateral insulated gate bipolar transistor (LIGBT) with SRFP fabricated in SOI with 2-m-thick BOX achieved good characteristics not only in the high BV of 580 V, but also in the fast switching of 280 ns. 7) However, there are no reports that a SOI micro-inverter IC achieved a higher BV than 700 V and a larger current capability than 3 A simultaneously.…”

Section: Introductionmentioning

confidence: 99%

High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC

Shiraki¹,

Takahashi²,

Yamada³

et al. 2012

We have successfully developed the record high blocking voltage of 750 V and the largest current capability of 4.5 A silicon-on-insulator (SOI) micro-inverter IC, which is made possible by the newly developed high voltage reliability technology and high-speed and low-dissipation extraction enhanced lateral insulated gate bipolar transistor (E2LIGBT). It has been found, for the first time, that the stable and reliable high blocking voltage of 760 V is assured by controlling the sheet-resistance of the polycrystalline silicon (poly-Si) layer of the scroll-shaped resistive field plate (SRFP). The high voltage and high reliability SOI power IC technology is expected as the key technology enabling 750 V 4.5 A micro-inverter IC for harsh applications such as automotive electronics.