2007
DOI: 10.1016/j.neucom.2006.11.028
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A high bit resolution FPGA implementation of a FNN with a new algorithm for the activation function

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Cited by 52 publications
(33 citation statements)
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“…The first comparison item is implementation area. The proposed FPGA-based intelligent hardware implementation [7,[10][11][12][13] is very suitable method for the semiconductor circuit elements.…”
Section: Resultsmentioning
confidence: 99%
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“…The first comparison item is implementation area. The proposed FPGA-based intelligent hardware implementation [7,[10][11][12][13] is very suitable method for the semiconductor circuit elements.…”
Section: Resultsmentioning
confidence: 99%
“…The execution time and hardware space used is excessively better on FPGA [7,9,10,13] when comparing the classical electronic chips. FPGA chips have endless reconfigurations advantages according to ASIC's, CPLD's or DSP's.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…In [5], the authors present an FPGA implementation of the reactive routing scheme for improving the performance of mobile ad-hoc networks using a 2-4-1 MLP ANN. Floating point representation was explored for an adaptive activation function and for the entire compute structure in [10], [11], providing better accuracy for the system. Among others, [7], [12] discuss the use of ANNs for hard-real-time embedded applications like fault-detection, and real-time tracking applications in automotive and defence systems.…”
Section: Related Workmentioning
confidence: 99%
“…The common use of the hyperbolic tangent and other sigmoid functions, though simple in terms of software, is very difficult to implement in hardware and has been the object of study of many researchers [5][6][7][8][9][10][11][12][13][14][15]. As a result of this difficulty, most of the implementations found in the literature use oversimplified activation functions [6,7,9].…”
Section: Introductionmentioning
confidence: 99%