A high bandwidth superscalar microprocessor for multimedia applications

Raam, F.M.; Agarwal, Ravinder; Malik, Kamil; Landman, Howard A.; Tago, H.; Teruyama, T.; Sakamoto, Tadashi; Yoshida, Toyohiko; Yoshioka, Shinichi; Fujimoto, Y.; Kobayashi, Toshiaki; Hiroi, T.; Oka, Masaaki; Ohba, A.; Suzuoki, M.; Tanaka, Yutaka; Yamamoto, Yasuyuki

doi:10.1109/isscc.1999.759231

Cited by 21 publications

(3 citation statements)

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“…The details were reported at ISSCC1999 [1][2] and at HOTCHIPS1999 [3]. It was the world's first 128-bit microprocessor with two sets of coprocessors based on floating-point functionality for graphics and animation.…”

Section: Emotion Enginementioning

confidence: 99%

Toward Future Computer Entertainment Systems

Kutaragi¹

2006

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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I. THE BIRTH OF COMPUTERSSixty years have passed since the birth of ENIAC, utilizing over 18,800 vacuum tubes; 35 years have passed from the birth of the world's first microprocessor the "4004", integrating more than 2300 transistors. During these years, dramatic advances have been made in semiconductor process technology. Today, the most advanced microprocessor integrates several hundreds of millions of transistors on a single silicon chip, and boasts computing power a million times greater than that of the first microprocessor. Also, thanks to advances in semiconductor process technology, downsizing of chips has progressed, making it possible for PCs to excel in various applications, and significant improvements have been made in computing. II. REAL-TIME COMPUTINGThe main thrust of general-purpose computers is to process various and broad office applications, precisely and efficiently. Realtime responsiveness is generally not important. As well, software systems for general-purpose computers became more and more complicated, "comfortable" operation that was natural in analog and mechanical systems has been gradually lost. Even with a PC that incorporates the latest microprocessor and memory system, users are frustrated by the computer system stalling when accessing large files such as encountered in moving images, and even worse, the system itself sometimes freezes. One of the reasons for such performance degeneration is that both microprocessors and operating systems have made continuous efforts to downsize existing systems, while coping with the inherited architectures of traditional main-frame computers. Today, a wide range of applications can be realized by software solutions on general-purpose computers instead of by dedicated hardware; thus many hardware solutions are being taken over by computer systems. This is a rational progression, brought about by technology. Nevertheless, as a result of operation becoming more complicated, and real-time responsiveness largely disappearing, instinctive and intuitive behaviours expected by human beings become more and more absent. The user is compelled to read through hundreds of pages of manuals to uncover procedures and protocols, or to attend special computer schools. However, such knowledge, however obtained, soon becomes outdated. This is one of the causes for human hesitation in adopting computers.On the other hand, when real-time responsiveness is emphasized, there are two elements that a human being can intuitively sense; One is the seamless continuity of motion that a human being cognitively feels to be real; and the other is the discernable predictability of the response time between action and reaction. Thus, currently, the frame rate required to allow consecutive still images to be perceived as a moving image is 24 frames per second, in the case of film, and 50 to 60 frames per second, in the case of NTSC/PAL TV systems. In the future, frame rate will be enhanced to become even higher for improving the fidelity of "expression". Researchers report that hum...

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Section: Emotion Enginementioning

confidence: 99%

Toward Future Computer Entertainment Systems

Kutaragi¹

2006

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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“…For example, in [1], [2] and [3] some possible architectures for mid-to-high-end embedded processors with SPM are described. Scratchpad memories, in these works, can act in cooperation with caches, either by taking the role of fast buffers for data transfer or by helping prevent cache pollution thanks to intelligent data management.…”

Section: Related Workmentioning

confidence: 99%

“…We next illustrate a polynomial-time algorithm to solve SPP, whose running time complexity is Θ(N · C 2 ). This is not too far from the Θ(M · C) complexity required to solve KP by dynamic programming, M with M ≤ N being the number of blocks and C again the SPM size (see [20]) 1 . At this point we would like to stress that the main advantage of our approach, when compared to the KP, is not that we solve a polynomial problem (SPP) instead of an NP-complete one (KP), since the time to solve the latter is smaller, but that we solve a much more general problem, as discussed above, in a comparable running time.…”

Section: Dynamic Programmingmentioning

confidence: 99%

Polynomial-time algorithm for on-chip scratchpad memory partitioning

Angiolini

Benini

Caprara

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main challenge in SPM design is mapping memory locations to scratchpad locations. This paper describes an algorithm to optimally solve such a mapping problem by means of Dynamic Programming applied to a synthesizable hardware architecture. The algorithm works by mapping segments of external memory to physically partitioned banks of an on-chip SPM; this architecture provides significant energy savings. The algorithm does not require any user-set bound on the number of partitions and takes into account partitioning overhead. Improving on previous solutions, execution time is polynomial in the input size. Strategies to optimize memory requirements and speed of the algorithm are exploited. Additionally, we integrate this algorithm in a complete and automated design, simulation and synthesis flow.

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