A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters

Erdmann, Christophe; Lowney, D.; Lynam, Adrian; Keady, Aidan; McGrath, John; Cullen, Edward; Breathnach, Daire; Keane, Denis; Lynch, Patrick; Torre, Marites De La; Torre, Ronnie De La; Lim, Peng; Collins, Anthony; Farley, Brendan; Madden, Lachlan

doi:10.1109/jssc.2014.2357432

Cited by 65 publications

(10 citation statements)

References 12 publications

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“…This type of joint technology has rapidly grown in demand with great engineering efforts for vertical interconnects in conjunction with through-silicon via (TSV) [ 9–13 ]. Thousands of microbumps solder joints are normally supported with two other types of joints, namely ball grid array (BGA) and flip-chip C-4 (or controlled collapse chip connection) solder joints to constitute the 3D ICs [ 14 ].…”

Section: Introductionmentioning

confidence: 99%

Intermetallic compounds in 3D integrated circuits technology: a brief review

Annuar

Mahmoodian

Hamdi

et al. 2017

Science and Technology of Advanced Materials

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The high performance and downsizing technology of three-dimensional integrated circuits (3D-ICs) for mobile consumer electronic products have gained much attention in the microelectronics industry. This has been driven by the utilization of chip stacking by through-Si-via and solder microbumps. Pb-free solder microbumps are intended to replace conventional Pb-containing solder joints due to the rising awareness of environmental preservation. The use of low-volume solder microbumps has led to crucial constraints that cause several reliability issues, including excessive intermetallic compounds (IMCs) formation and solder microbump embrittlement due to IMCs growth. This article reviews technologies related to 3D-ICs, IMCs formation mechanisms and reliability issues concerning IMCs with Pb-free solder microbumps. Finally, future outlook on the potential growth of research in this area is discussed.

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Section: Introductionmentioning

confidence: 99%

Intermetallic compounds in 3D integrated circuits technology: a brief review

Annuar

Mahmoodian

Hamdi

et al. 2017

Science and Technology of Advanced Materials

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“…Additionally, the results of this figure demonstrate that reducing the number of active RF chains can have substantial benefits in the overall power consumption. This is a direct consequence of the power consumed by a) the additional components required per each RF chain (P cir and P DAC , P ADC ), b) the additional signal processing load (P BB ) and c) the increased power consumption in the data interfaces (P int ) due to the increased amount of data generated [48]. The energy efficiency ξ in (35) is shown vs. M in Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Characteristics P ADC = 233 mW [46] b ADC = 12 bits, S ADC = 125 MSPS P DAC = 232 mW [47] b DAC = 14 bits, S DAC = 125 MSPS p int = 25 mW/Gbps [48] Parallel interface LVDS P cir = 1 W [33] -…”

Section: Parametermentioning

confidence: 99%

Reduced Switching Connectivity for Large Scale Antenna Selection

García‐Rodríguez

Masouros

Rulikowski

2017

IEEE Trans. Commun.

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In this paper, we explore reduced-connectivity radio frequency (RF) switching networks for reducing the analog hardware complexity and switching power losses in antenna selection (AS) systems. In particular, we analyze different hardware architectures for implementing the RF switching matrices required in AS designs with a reduced number of RF chains. We explicitly show that fully-flexible switching matrices, which facilitate the selection of any possible subset of antennas and attain the maximum theoretical sum rates of AS, present numerous drawbacks such as the introduction of significant insertion losses, particularly pronounced in massive multiple-input multiple-output (MIMO) systems. Since these disadvantages make fully-flexible switching suboptimal in the energy efficiency sense, we further consider partially-connected switching networks as an alternative switching architecture with reduced hardware complexity, which we characterize in this work. In this context, we also analyze the impact of reduced switching connectivity on the analog hardware and digital signal processing of AS schemes that rely on received signal power information. Overall, the analytical and simulation results shown in this paper demonstrate that partially-connected switching maximizes the energy efficiency of massive MIMO systems for a reduced number of RF chains, while fully-flexible switching offers sub-optimal energy efficiency benefits due to its significant switching power losses.

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“…To measure the power consumption of a 3D-IC, the straight forward method is to fabricate and set up a measuring system [15]. However, it is difficult to obtain such a system, especially designing and fabricate the chip is expensive and designers want to estimate the value before sending to production.…”

Section: Power Modeling For 3d Network-on-chipmentioning

confidence: 99%

Thermal distribution and reliability prediction for 3D Networks-on-Chip

Dang¹,

Ahmed²,

Abdallah³

et al. 2020

JCSCE

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As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Blackâ€™s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based design. We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature.

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A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters

Cited by 65 publications

References 12 publications

Intermetallic compounds in 3D integrated circuits technology: a brief review

Intermetallic compounds in 3D integrated circuits technology: a brief review

Reduced Switching Connectivity for Large Scale Antenna Selection

Thermal distribution and reliability prediction for 3D Networks-on-Chip

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