A Hardware/Software Approach for Database Query Acceleration with FPGAs

Sukhwani, Bharat; Thoennes, Mathew; Min, Hyun Jin; Dube, Parijat; Brezzo, Bernard; Asaad, Sameh; Dillenberger, Donna

doi:10.1007/s10766-014-0327-4

Cited by 26 publications

(9 citation statements)

References 20 publications

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“…Cai et al utilized the capability of Vivado HLS to transform a software face recognition program to a corresponding hardware design based on Zynq platform [9,11]. Their intention was to improve the face detection performance, and the result indicates the performance was improved by up to 80% after migrating the computation onto the hardware.…”

Section: Related Workmentioning

confidence: 99%

“…Now, As opposed to the low-level design approach, Model Based design for FPGA are one of the methods that are based of high-level modeling for image and video processing applications on a very higher level of abstraction. Many various industrial and academic design approaches are available such as Simulink/ Xilinx System generator models, which can convert automatically into a hardware (VHDL) description [10,11].…”

Section: Related Workmentioning

confidence: 99%

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Fast FPGA Prototyping based Real-Time Image and Video Processing with High-Level Synthesis

Ghodhbani¹,

Horrigue²,

Saidani³

et al. 2020

IJACSA

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Programming in high abstraction level is known by its benefits. It can facilitate the development of digital image and video processing systems. Recently, high-level synthesis (HLS) has played a significant role in developing this field of study. Real time image and video Processing solution needing high throughput rate are often performed in a dedicated hardware such as FPGA. Previous studies relied on traditional design processes called VHDL and Verilog and to synthesize and validate the hardware. These processes are technically complex and time consuming. This paper introduces an alternative novel approach. It uses a Model-Based Design workflow based on HDL Coder (MBD), Vision HDL Toolbox, Simulink and MATLAB for the purpose of accelerating the design of image and video solution. The main purpose of the present paper is to study the complexity of the design development and minimize development time (Time to market: TM) of conventional FPGA design. In this paper, the complexity of the development™ can be reduced by 60% effectively by automatically generating the IP cores and downloading the modeled design through the Xilinx tools and give more advantages of FPGA related to the other devices like ASIC and GPU.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Fast FPGA Prototyping based Real-Time Image and Video Processing with High-Level Synthesis

Ghodhbani¹,

Horrigue²,

Saidani³

et al. 2020

IJACSA

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“…Academics and industry are beginning to explore some new ways to accelerate the performance of data processing through software/hardware co-design. Instructionlevel optimization [16], coprocessor query optimization [17,18], hardware customization [19], workload hardware migration [20], increasing hardware-level parallelism [21], hardware-level operators [22], and so on are used to provide hardware-level performance optimization. However, the differences between the new processor and x86 processor fundamentally change the assumptions of traditional database software design on hardware.…”

Section: System Architecture and Design Schemes In Platforms With Newmentioning

confidence: 99%

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Pan

Zhang

et al. 2018

Data Sci. Eng.

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Hardware techniques and environments underwent significant transformations in the field of information technology, represented by high-performance processors and hardware accelerators characterized by abundant heterogeneous parallelism, nonvolatile memory with hybrid storage hierarchies, and RDMA-enabled high-speed network. Recent hardware trends in these areas deeply affect data management and analysis applications. In this paper, we first introduce the development trend of the new hardware in computation, storage, and network dimensions. Then, the related research techniques which affect the upper data management system design are reviewed. Finally, challenges and opportunities are addressed for the key technologies of data management and analysis in new hardware environments.

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“…Besides the proposals of ETH Zurich, Dennl et al [3] presented concepts for on-the-fly hardware acceleration of SQL queries with restriction, aggregation, and join operators to execute queries on the FPGA. Sukhwani et al [14] proposed in their solution that the analytical queries are moved from the host running the workload to the composable accelerators.…”

Section: Introductionmentioning

confidence: 99%

MASCARA-FPGA cooperation model: Query Trimming through accelerators

Huu

d’Orazio

Casseau

et al. 2021

33rd International Conference on Scientific and Statistical Database Management

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The use of Field Programmable Gate Arrays (FPGA) has become attractive in recent years to accelerate database analysis. Meanwhile, Semantic Caching (SC) is a technique for optimizing the evaluation of database queries by exploiting the knowledge and resources contained in the queries themselves. Organizing SC on FPGA is relevant in terms of response time and quality of results to increase system performance. To make SC scalable on FPGAs, we have proposed a ModulAr Semantic CAching fRAmework (MAS-CARA) in which relevant stages or modules could be convertible as accelerators on FPGAs. Therefore, in this paper, we aim to present a complementary query processing platform based on the cooperation model between MASCARA and FPGA. This novel approach extends the advantage of the classical SC, which is mainly based on Central Processing Unit (CPU), by offloading computationally intensive phases to FPGA. Moreover, MASCARA-FPGA presents the workflow of query rewriting and partial query execution in a pipelined execution model where multiple accelerators can run in parallel. In our experiments, the Query Trimming can reduce the response time by up to 3.96 times with only one accelerator used.

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A Hardware/Software Approach for Database Query Acceleration with FPGAs

Cited by 26 publications

References 20 publications

Fast FPGA Prototyping based Real-Time Image and Video Processing with High-Level Synthesis

Fast FPGA Prototyping based Real-Time Image and Video Processing with High-Level Synthesis

The New Hardware Development Trend and the Challenges in Data Management and Analysis

MASCARA-FPGA cooperation model: Query Trimming through accelerators

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