A Hardware in the Loop Benchmark Suite to Evaluate NIST LWC Ciphers on Microcontrollers

Renner, Sebastian; Pozzobon, Enrico; Mottok, Jürgen

doi:10.1007/978-3-030-61078-4_28

Cited by 8 publications

(2 citation statements)

References 6 publications

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“…The hardware implementation of the SpoC AEAD algorithm was verified through simulation using Xilinx ISE Simulator (ISIM). The test vectors for the simulation were obtained from [23]. For the encryption routine, the key and the nonce use the same 128-bit value (128'h000102030405060708090A0B0C0D0E0F0) while the associated data (ad) and plaintext also use the same 64-bit value (64'h0001020304050607).…”

Section: Hardware Results and Verificationmentioning

confidence: 99%

The Hardware Implementation of NIST Lightweight Cryptographic Candidate SpoC for loT Devices

Gookyi¹,

Ryoo²

2021

Ijasc

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Background/Objectives: This paper presents the hardware implementation of SpoC Lightweight Cryptography (LWC) candidate for low-cost devices. Methods/Statistical analysis: The proposed hardware implementation of the SpoC Authenticated Encryption with Associated Data (AEAD) is capable of both encryption and decryption. The design was implemented on the Virtex-4 Field FPGA using Xilinx ISE Design Suite. The synthesis results reported 951 slices at 246.61 MHz maximum clock frequency. The encryption and decryption routines take 589 and 590 cycles. Findings: This work used 30% fewer LUTs for both encryption and decryption as compared to the existing work. The decrease in area in this work is a result of the optimization of the implementation for low-cost devices while the existing work implemented the basic iterative architecture without optimizing. This work achieved almost two times the frequency of the existing SpoC implementation. The existing SpoC implementation used 150 fewer cycles as compared to this work. This is because this work implemented the SpoC using extra registers in other to reduce the critical path which increases the frequency. Improvements/Applications: For future works, the proposed SpoC AEAD will be combined with other security protocols to form a lightweight cryptographic System-on-Chip (SoC).

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Section: Hardware Results and Verificationmentioning

confidence: 99%

The Hardware Implementation of NIST Lightweight Cryptographic Candidate SpoC for loT Devices

Gookyi¹,

Ryoo²

2021

Ijasc

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“…Renner et al [RPM20] present a hardware-in-the-loop benchmarking framework for the LWC process; since their focus is the framework, they use the source code submitted for a given algorithm. Their work is based on use of a Kendryte K210 core.…”

Section: Software: Api Table 4 Tablementioning

confidence: 99%

RISC-V Instruction Set Extensions for Lightweight Symmetric Cryptography

Cheng

Großschädl

Marshall³

et al. 2022

TCHES

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The NIST LightWeight Cryptography (LWC) selection process aims to standardise cryptographic functionality which is suitable for resource-constrained devices. Since the outcome is likely to have significant, long-lived impact, careful evaluation of each submission with respect to metrics explicitly outlined in the call is imperative. Beyond the robustness of submissions against cryptanalytic attack, metrics related to their implementation (e.g., execution latency and memory footprint) form an important example. Aiming to provide evidence allowing richer evaluation with respect to such metrics, this paper presents the design, implementation, and evaluation of one separate Instruction Set Extension (ISE) for each of the 10 LWC final round submissions, namely Ascon, Elephant, GIFT-COFB, Grain-128AEADv2, ISAP, PHOTON-Beetle, Romulus, Sparkle, TinyJAMBU, and Xoodyak; although we base the work on use of RISC-V, we argue that it provides more general insight.

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