A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding

Abstract

Variable block size motion estimation has contributed greatly to achieving an optimal interframe encoding, but involves high computational complexity and huge memory access, which is the most critical bottleneck in ultra-high-definition video encoding. This article presents a hardware-efficient block matching algorithm with an efficient hardware design that is able to reduce the computational complexity of motion estimation while providing a sustained and steady coding performance for high-quality video encoding. A three-level memory organization is proposed to reduce memory bandwidth requirement while supporting a predictive common search window. By applying multiple search strategies and early termination, the proposed design provides 1.8 to 3.7 times higher hardware efficiency than other works. Furthermore, on-chip memory has been reduced by 96.5% and off-chip bandwidth requirement has been reduced by 39.4% thanks to the proposed three-level memory organization. The corresponding power consumption is only 198mW at the highest working frequency of 500MHz. The proposed design is attractive for high-quality video encoding in real-time applications with low power consumption.

Hardware motion estimation methods survey and example real-time architecture design

“…An efficient block matching algorithm and a three-level memory organization were proposed [10]. A large search range does not necessarily improve the coding performance, while a small search range can reduce the search complexity without significantly reducing the search accuracy.…”

Motion estimation algorithm and architecture survey

“…An efficient block level matched architecture hardware design and its supporting algorithm J. Zheng et al presented a hardware-efficient BMA and its hardware design [12]. The algorithm is based on three aspects including (1) predict the search center; (2) early termination, and (3) pixel downsampling.…”

“…The result shows that it achieved better performance in resource consumption and coding time. In J. Zheng et al presented a hardware-efficient motion estimation algorithm [12]. By applying a three-level memory organization, multiple search strategies, and early termination, this algorithm reduces the computation complexity while maintaining a stable coding performance.…”

An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec

“…The final implementation results show that the smart Motion estimation controller architecture using bandwidth control scheme achieves an average bandwidth reduction of 56.08% compared with previous non-bandwidth ondemand Motion Estimation designs for high-definition (HD) videos. Zheng et al (2019b) presented an effectual hardware matching block as an effectual design for the hardware, which was capable of eliminating the complexity of calculation in motion approximation to implement a sustained and constant coding performance for video coding with maximum quality. A three-level organisation memory was established to eliminate bandwidth memory requirements, to help a forecast of the general search window.…”

“…Zheng et al (2019b) presented an effectual hardware matching block as an effectual design for the hardware, which was capable of eliminating the complexity of calculation in motion approximation to implement a sustained and constant coding performance for video coding with maximum quality. A three-level organisation memory was established to eliminate bandwidth memory requirements, to help a forecast of the general search window.…”