A hardware-based cache pollution filtering mechanism for aggressive prefetches

Zhuang, Xin; Lee, H.-H.S.

doi:10.1109/icpp.2003.1240591

Cited by 45 publications

(46 citation statements)

References 8 publications

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“…Prior papers on prefetch filtering propose techniques to detect and eliminate prefetches that are found to be useless in the past [37,39,21]. However, conservative prefetch filtering techniques cannot filter out all useless prefetches, yet aggressive ones can remove many useful prefetches [18].…”

Section: Prefetch Filteringmentioning

confidence: 99%

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Prefetch-aware shared resource management for multi-core systems

Ebrahimi

Lee

Mutlu

et al. 2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

103

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Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these shared resources; however, none of them take into account prefetch requests. Without prefetching, significant performance is lost, which is why existing systems prefetch. By not taking into account prefetch requests, recent shared-resource management proposals often significantly degrade both performance and fairness, rather than improve them in the presence of prefetching.This paper is the first to propose mechanisms that both manage the shared resources of a multi-core chip to obtain highperformance and fairness, and also exploit prefetching. We apply our proposed mechanisms to two resource-based management techniques for memory scheduling and one source-throttling-based management technique for the entire shared memory system. We show that our mechanisms improve the performance of a 4-core system that uses network fair queuing, parallelism-aware batch scheduling, and fairness via source throttling by 11.0%, 10.9%, and 11.3% respectively, while also significantly improving fairness.

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Section: Prefetch Filteringmentioning

confidence: 99%

“…We find that our proposals are complementary to prefetch filtering. For example, P-NFQ increases system performance by 11.1%/8.2% (HS/WS) while reducing max slowdown by 10.9% on a baseline where a state-of-the-art hardware filtering mechanism [39] is used with NFQ + HPAC.…”

Section: Prefetch Filteringmentioning

confidence: 99%

Prefetch-aware shared resource management for multi-core systems

Ebrahimi

Lee

Mutlu

et al. 2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

103

View full text Add to dashboard Cite

show abstract

“…The first group determines whether proceeds the prefetching access or not for each predicted address. Zhuang et al [10] proposed a technique that estimates the accuracy of each address prediction. The history regarding whether previous prefetched lines were actually accessed are stored in a table of 2-bit saturation counters.…”

Section: Adaptive Prefetching Techniquesmentioning

confidence: 99%

“…Thus, recent prefetch techniques generally involve mechanisms that dynamically optimize the amount of prefetching. However, in the existing adaptive prefetching, the accuracy of address prediction is used as a metric because the current data in the cache should be valuable [10]- [12]. This is not always true in LLC because aggressive depths and widths of the effective prefetching are gained in exchange of accuracy.…”

Section: Introductionmentioning

confidence: 99%

Using Cacheline Reuse Characteristics for Prefetcher Throttling

Irie

Miyoshi

Honjo

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs' working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+), which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256 KB LLC, 1.8% over the latest prefetcher throttling, and 0.5% over our previous CCCPO. Moreover, it showed superior stability compared to related works, while lowering the hardware cost.

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“…The Markov prefetcher [21] is an example of such correlation prefetching. Other prefetchers rely on the compiler to provide prefetch hints [42,45]. These software based techniques are good at predicting misses due to pointer de-references.…”

Section: Related Workmentioning

confidence: 99%

Improving cache locality for thread-level speculation

Fung¹,

Steffan²

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the performance of an individual program. However, with such speculatively-parallel execution the cache locality once enjoyed by the original uniprocessor execution is significantly disrupted: for TLS execution on a four-processor CMP, we find that the data-cache miss rates are nearly four-times those of the uniprocessor case, even though TLS execution utilizes four private data caches.We break down the TLS cache locality problem into instruction and data cache, execution stages, and parallel access patterns, and propose methods to improve cache locality in each of these areas. We find that for parallel regions across 13 SPECint applications our simple and low-cost techniques reduce data-cache misses by 38.2%, improve performance by 12.8%, and significantly improve scalability-further enhancing the feasibility of TLS as a way to capitalize on future CMPs.ii

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A hardware-based cache pollution filtering mechanism for aggressive prefetches

Cited by 45 publications

References 8 publications

Prefetch-aware shared resource management for multi-core systems

Prefetch-aware shared resource management for multi-core systems

Using Cacheline Reuse Characteristics for Prefetcher Throttling

Improving cache locality for thread-level speculation

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