A Hardware Architecture for SVPWM Digital Control With Variable Carrier Frequency and Amplitude

Benedetto, Luigi Di; Donisi, Andrea; Licciardo, Gian Domenico; Rubino, Alfredo

doi:10.1109/tii.2021.3124840

Cited by 7 publications

(4 citation statements)

References 21 publications

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“…2) T IM E DIV ISOR block: This block divides the three dwell-times in the seven sub-intervals of the COU N T ER block (see Fig. 6) as follows [20]:…”

Section: T Im E Calcu Lat or Macro-blockmentioning

confidence: 99%

“…However, there are several effort to implement SVPWM technique in FPGA controllers in order to simplify and to reduce the complexity of the algorithm, and there are solutions based on CORDIC algorithms [19] or on Look-Up table approaches [20], [21] and that can use DSPs [22] or external flash memory with an external signal reference [23]. However, there are some drawbacks: firstly, in the case of the external PCs or DSPs, one needs powerful hardware that limits the fields of applications, like stand-alone applications because SVPMW signal generator requires external reference signals; secondly, although hardware architectures based on LUT reduce the complexity and do not require external resources, the variations of the three-phase output waveform are only possible for multiple values of the reference value [20], [21], [24]. Moreover, FPGA manufactures provide FPGA core Intellectual Property modules to implement SVPWM technique, but they cannot be modified in order to optimize the resource for a specific applications as well as to improve the algorithm.…”

Section: Introductionmentioning

confidence: 99%

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A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

Di Benedetto,

Donisi,

Liguori

et al. 2024

IEEE J. Emerg. Sel. Topics Power Electron.

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A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed and based on a novel algorithm for the evaluation of the dwell-times. Indeed, the complexity of the calculation of trigonometric functions is solved introducing a Taylor series decomposition and using a convenient definition of the space vector α − β plane. Our architecture can modify the dwell-times as function of the carrier and switching frequencies, of the phase and of the modulation index. Comparing to other techniques, it avoids the use of external reference voltages as well as of the pre-calculated dwelltimes, like for the LUT-based architectures. Although it can be implemented in several logic devices, an Altera Cyclone V Field Programmable Gate Array is used as a digital controller of a three-phase power inverters and its resources are the 16% and 2%, respectively, of the Look-Up Tables and of the Flip Flops. Several cases are studied in order to show the goodness of the output waveforms during the real-time variations of the inputs.

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“…2) T IM E DIV ISOR block: This block divides the three dwell-times in the seven sub-intervals of the COU N T ER block (see Fig. 6) as follows [20]:…”

Section: T Im E Calcu Lat or Macro-blockmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

Di Benedetto,

Donisi,

Liguori

et al. 2024

IEEE J. Emerg. Sel. Topics Power Electron.

Self Cite

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“…However, the modulation algorithm becomes complex as the number of devices increases. As the three-dimensional sinusoidal pulse width modulation (3DSVPMW) method has higher DC voltage utilization than the carrier-based pulse width modulation (CBPWM) method and is easy to implement digitally, the former is more valued in practical applications [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

A simplified space vector pulse width modulation method for a three‐level four‐leg inverter considering the neutral point potential balance

Zhang

Chen

et al. 2023

IET Power Electronics

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This paper presents a simple three-dimensional space vector modulation method in gh𝜸 coordinates for a three-level four-leg neutral-point-clamped inverter. The idea uses redundant vectors as centre points to establish two-level space vector diagrams simplifying the original space, the first sector of which is designated as subspaces, where a modulation process is implemented. The duty cycle and all possible switching sequences in a tetrahedron can be calculated automatically without manual storage and can avoid a full-scale search process. Additionally, the neutral point potential can be balanced by three types of charge through cancellation. Such features enable the inverter to demonstrate good performance under closed-loop control. Moreover, the proposed method can be applied to a multilevel inverter. Simulation and experimental results demonstrate the effectiveness of the proposed concept.

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“…We show our proposal by using FPGA digital controller integrated in a power AC/DC converter for asynchronous motor driving, but it can be also adapted for micro-controllers. The novelties introduced in this paper compared to others solutions [25], [26], that are based on the storage of precalculated dwell-times are as follows:…”

Section: Introductionmentioning

confidence: 99%

Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

et al. 2022

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A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed. Its features are the reduced hardware resources and the real-time variation of the values of the carrier and switching frequencies, of the phase and of the amplitude of the three-phase output voltages in addition to not require external reference signals or further processors, like Digital Signal Processor. The basic idea is to pre-calculate a set of normalized dwell-time for only one sixth of the α − β-plane and, then, to reconstruct through our architecture the effective dwell-times and the right inverter configurations by an optimized management of the memory. The architecture is implemented in a Field Programmable Gate Array Cyclone V using the 6% and the 1.01%, respectively, of the Look-Up Tables and of the Flip Flops and the experimental measurements show the goodness of the generated waveforms and the high numbers of degrees of freedom without the demand of Digital Signal Processor or Personal Computer.INDEX TERMS Digital controller, field programmable gate array, space vector pulse width modulation, three-phase DC/AC power converter.

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A Hardware Architecture for SVPWM Digital Control With Variable Carrier Frequency and Amplitude

Cited by 7 publications

References 21 publications

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

A simplified space vector pulse width modulation method for a three‐level four‐leg inverter considering the neutral point potential balance

Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

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