Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

Abstract

A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed. Its features are the reduced hardware resources and the real-time variation of the values of the carrier and switching frequencies, of the phase and of the amplitude of the three-phase output voltages in addition to not require external reference signals or further processors, like Digital Signal Processor. The basic idea is to pre-calculate a set of normalized dwell-time for only one sixth of the α − β-plane and, then, to reconstruct through our architecture the effective dwell-times and the right inverter configurations by an optimized management of the memory. The architecture is implemented in a Field Programmable Gate Array Cyclone V using the 6% and the 1.01%, respectively, of the Look-Up Tables and of the Flip Flops and the experimental measurements show the goodness of the generated waveforms and the high numbers of degrees of freedom without the demand of Digital Signal Processor or Personal Computer.INDEX TERMS Digital controller, field programmable gate array, space vector pulse width modulation, three-phase DC/AC power converter.

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

“…instead, starting from (10b) or (13b), we obtain the new counter index, j, as follows: block, as explained in Section III-C. This block controls the multiplexer with the M U X signal: indeed, it selects the configuration of the top transistors for each sub-interval [21]. Fig.…”

“…In particular, each signal has a delay when a rising edge appears and it is configurable (in the Section IV it is 500ns). Before to send the three signals to the DEAD T IM E block, the signals of the B and C legs of the inverter can be switched in order to impose either a clockwise or a counterclockwise direction of rotation for − −− → V REF [21].…”

“…However, there are several effort to implement SVPWM technique in FPGA controllers in order to simplify and to reduce the complexity of the algorithm, and there are solutions based on CORDIC algorithms [19] or on Look-Up table approaches [20], [21] and that can use DSPs [22] or external flash memory with an external signal reference [23]. However, there are some drawbacks: firstly, in the case of the external PCs or DSPs, one needs powerful hardware that limits the fields of applications, like stand-alone applications because SVPMW signal generator requires external reference signals; secondly, although hardware architectures based on LUT reduce the complexity and do not require external resources, the variations of the three-phase output waveform are only possible for multiple values of the reference value [20], [21], [24]. Moreover, FPGA manufactures provide FPGA core Intellectual Property modules to implement SVPWM technique, but they cannot be modified in order to optimize the resource for a specific applications as well as to improve the algorithm.…”

Design and Implementation of an Efficient Hardware Coprocessor IP Core for Multi-axis Servo Control Based on Universal SoC

“…FPGA is suitable for medium and high-end motor control applications due to its unique parallelism [9,10]. In recent years, certain vector control algorithms have been applied to FPGA to realize its acceleration [11][12][13][14][15]. Loop operation of vector control through FPGA has also been suitable for medium and high-end motor control applications due to its unique parallelism [9,10].…”

“…Loop operation of vector control through FPGA has also been suitable for medium and high-end motor control applications due to its unique parallelism [9,10]. In recent years, certain vector control algorithms have been applied to FPGA to realize its acceleration [11][12][13][14][15]. Loop operation of vector control through FPGA has also been applied [16][17][18][19][20], greatly improving the operation speed of the current loop.…”