A hardware accelerated implementation of the IEEE 802.15.3 MAC protocol

Abstract

We present a hardware/software implementation of the IEEE 802.15.3 MAC protocol. Processing-intensive and time-critical protocol tasks are handled by a protocol accelerator that is integrated on-chip with a 32-bit generalpurpose processor in order to achieve a moderate (20-40 MHz) system clock frequency. This enables low-power wireless devices compliant with this standard, providing high data rate, multimedia communication.One of the main tasks of the protocol accelerator is to analyze received or transmitted beacons. Based on the channel time allocations broadcast in the beacon and frame information stored in a hardware transmission queue, frames are transmitted without immediate control of the processor. Other features of the protocol accelerator include CRC generation, handling of immediate acknowledgment frames, and direct memory access.

System/network design-space exploration based on TLM for networked embedded systems

“…Figure 2 shows a simple representation of a NES and highlights the presence of system and network parts. The system usually consists of a CPU, a memory to store application code and data, one or more network interfaces, I/O interfaces for data acquisition and user interaction, and other components (i.e., ASIC's, FPGA's) designed to efficiently perform specific functions [Benini et al 2003;Dietterle and Kraemer 2002]. An application-specific SW is deployed over this HW architecture, often together with an operating system, which bridges HW and SW components.…”