A half-micron CMOS logic generation

Koburger, Charles W.; Clark, William F.; Adkisson, J.; Adler, E.L.; Bakeman, P.; Bergendahl, A. S.; Botula, A.; Chang, Wen-Hao; Davari, B.; Givens, J.H.

doi:10.1147/rd.391.0215

Cited by 35 publications

(3 citation statements)

References 8 publications

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“…For off-chip interconnections over the last five decades, I/O interconnections grew from tens of I/O interconnections to about several thousands of I/O interconnections for the most complex die manufactured today. Figure 1(a) shows 3D technology evolution for silicon chips, packages, and printed wiring boards (PWBs), along with the resulting relative I/O interconnection density for silicon 3D circuits, chip stacking, and silicon packaging, as well as for ceramic and organic packaging [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. It is interesting to note that as new package form factors have entered production (such as thin-film sequential buildup technology on organic packages, thin film on ceramic packages, and wire-bonding chip stacks on organic or ceramic packages), these system-integration solutions have had severe interconnection density limitations that are on the order of thousands of interconnections (10 3 /cm 2 ).…”

Section: D Microelectronics Historical Evolutionmentioning

confidence: 99%

Three-dimensional silicon integration

et al. 2008

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Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (,10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

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Section: D Microelectronics Historical Evolutionmentioning

confidence: 99%

Three-dimensional silicon integration

et al. 2008

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“…8, 0.5, 0.35 Koburger et al (1995) by permission of IBM dielectric is oxide, and it is planarized by CMP. We will first discuss multilevel metallization for submicron technologies (0.…”

Section: Multilevel Metallizationmentioning

confidence: 99%

Multilevel Metallization

2010

Introduction to Microfabrication

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“…The quarter century of progress in IC technology captured by the phrase "Moore's law" has been characterized by substantial decreases in the size and spacing of active and passive structures such as transistors and their interconnecting wires, accompanied by increases in chip complexity, size, and speed of operation [3]. In recent years, these advances have also necessitated an increase in the number of metal layers connecting the devices within the chip, and chip inputs and outputs, or I/Os, that are needed to connect the different chips in a system [4] and the use of "flip-chip" packaging methods. Dense "metal fill" patterns inserted in all areas not populated with signal wires are commonly used to optimize chemical-mechanical polishing processes.…”

Section: Trends and Needs For Test And Back-side Analysis In Silicon mentioning

confidence: 99%

Picosecond imaging circuit analysis

2000

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Picosecond imaging circuit analysis A newly developed optical method for noninvasively measuring the switching activity of operating CMOS integrated circuit chips is described. The method, denoted as picosecond imaging circuit analysis (PICA) can be used to characterize the gate-level performance of such chips and identify the locations and nature of their operational faults. The principles underlying PICA and examples of its use are discussed.

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A half-micron CMOS logic generation

Cited by 35 publications

References 8 publications

Three-dimensional silicon integration

Three-dimensional silicon integration

Multilevel Metallization

Picosecond imaging circuit analysis

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