9th EUROMICRO Conference on Digital System Design (DSD'06) 2006
DOI: 10.1109/dsd.2006.7
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A Graph Based Algorithm for Data Path Optimization in Custom Processors

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Cited by 5 publications
(6 citation statements)
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“…Table 2 compares the total number of FPGA Logic Elements of the initial data path at the second column, which is produced by Spark Tool, and the data paths, which are the output of three optimizer algorithms. In order to compare our new refinement algorithm with other algorithms, we implemented Graph Based Algorithm (GBA) presented in [10] in our optimizer block in lieu of our refinement algorithm. To make a fair comparison, we provide identical conditions and constraints for all algorithms.…”
Section: Resultsmentioning
confidence: 99%
See 2 more Smart Citations
“…Table 2 compares the total number of FPGA Logic Elements of the initial data path at the second column, which is produced by Spark Tool, and the data paths, which are the output of three optimizer algorithms. In order to compare our new refinement algorithm with other algorithms, we implemented Graph Based Algorithm (GBA) presented in [10] in our optimizer block in lieu of our refinement algorithm. To make a fair comparison, we provide identical conditions and constraints for all algorithms.…”
Section: Resultsmentioning
confidence: 99%
“…At first, the CDFG is used by the algorithm and is converted to a weighted directed acyclic graph (DAG).The conversion algorithm of CDFG to DAG is described in [10]. Then all paths from source nodes to sink node are extracted and sorted in a list with respect to their path lengths.…”
Section: Methodsmentioning
confidence: 99%
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“…The derived required number of source operand transfers determines the number of register file output ports and the number of source busses, where the number of destination operand transfers translates into register file input ports and the destination buses [1]. The connection resources are allocated in greedy manner: output ports of all register files are connected to all source buses and input ports are connected to all destination busses.…”
Section: Introductionmentioning
confidence: 99%
“…The heuristics use required number of source and destination operands and number of output and input ports for the storage elements available in the CL [Trajkovic et al, 2006].…”
Section: Initial Allocationmentioning
confidence: 99%