Automatic Data Path Generation from C code for Custom Processors

Trajković, Jelena; Gajski, Daniel D.

doi:10.1007/978-0-387-72258-0_10

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…They attempted to optimize only the critical path whereas by considering other paths, more optimizations are obtainable. Trajkovic and Gajski in [11] obtained an even better optimization by taking the data dependency between basic blocks into account.…”

Section: Related Workmentioning

confidence: 97%

Data path refinement algorithm in high-level synthesis based on dynamic programming

Rahimi

Mohammadi

Foroughi

2009

2009 International Conference on Innovations in Information Technology (IIT)

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As CMOS technology scales down into the deep-submicron domain, the cost of design, complexity and customization for Systems-On-Chip (SoCs) is rapidly increasing due to the inefficiency of traditional CAD tools. In this paper we present a new interactive refinement algorithm in high-level synthesis, based on dynamic programming, which maximizes resource optimization in data path. We start by quantifying the properties of the given application C code in terms of control data flow graph (CDFG), available parallelism and other metrics. We then apply designer guided constraints to a data path refinement algorithm for an initial data path. It attempts to reduce the number of the most expensive components while meeting the constraints. The experimental results show that not only the refined data path outperforms data paths refined by other heuristic methods, but also presents lower cost, less overhead and can be generated in less time.

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Section: Related Workmentioning

confidence: 97%

Data path refinement algorithm in high-level synthesis based on dynamic programming

Rahimi

Mohammadi

Foroughi

2009

2009 International Conference on Innovations in Information Technology (IIT)

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“…In [124] an algorithm is presented that maps an application on a given datapath by performing scheduling and binding simultaneously. In [125] two algorithms are presented, the first algorithm starts with an architecture that supports maximum parallelism for implementation of the input C code and iteratively refines it until an efficient resource utilization The other algorithm is used to choose the priority of application basic blocks for optimization.…”

Section: No Instruction Set Computer (Nisc)mentioning

confidence: 99%

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Qadri¹,

Gujarathi²,

McDonald-Maier³

2009

JCP

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Abstract-The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas.

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Exhaustive Data Path Optimization in High-Level Synthesis through Area Improvement

Rahimi

Mohammadi

Ranjbar

2009

2009 Fourth International Conference on Computer Sciences and Convergence Information Technology

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Automatic Data Path Generation from C code for Custom Processors

Cited by 3 publications

References 11 publications

Data path refinement algorithm in high-level synthesis based on dynamic programming

Data path refinement algorithm in high-level synthesis based on dynamic programming

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Exhaustive Data Path Optimization in High-Level Synthesis through Area Improvement

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