A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications

Pathak, Varsha; Saini, Gaurav

doi:10.1016/j.procs.2017.12.105

Cited by 26 publications

(8 citation statements)

References 11 publications

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“…Djeffal et al [21] proposed a dual material surrounded gate MOSFET of 10 nm for digital applications. The advantages of DMSG MOSFET's (Fig.…”

Section: Device Structure and Dimensionsmentioning

confidence: 99%

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

Mendiratta¹,

Tripathi²

2020

J. Semicond.

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CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current. To reduce the short channel effects new designs and technologies are implemented. Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET. Silicon-based MOSFET design can be used in a harsh environment. It has been used in various applications such as in detecting biomolecules. The increase in number of gates increases the current drive capability of transistors. GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region. It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit. Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of I ON/I OFF ratio. In this paper, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node. A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of I OFF, subthreshold slope and DIBL values. The analog/RF performance is analyzed for transconductance, effective transistor capacitances, stability factor and critical frequency. The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/ biomedical applications.

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“…Djeffal et al [21] proposed a dual material surrounded gate MOSFET of 10 nm for digital applications. The advantages of DMSG MOSFET's (Fig.…”

Section: Device Structure and Dimensionsmentioning

confidence: 99%

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

Mendiratta¹,

Tripathi²

2020

J. Semicond.

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“…An excellent transport efficiency of this JLSDGM device is portrayed by its high g m (max) which is suitably applicable for analog based applications. The I ON and g m (max ) magnitude of the JLSDGM device with 8 nm gate length have been compared to different structures of double-gate transistor from previous studies [50,51] as shown in Figure 11. Based on the comparison, it is shown that the current study (JLSDGM) has demonstrated the highest I ON and g m magnitudes compared to other double-gate structure technology.…”

Section: Fig 10 Plot Of Transconductance Versus Gate Lengthmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

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Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

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“…In order to solve this problem, a study was conducted to use high-k materials as the gate oxide film [17][18][19]. In addition, many structural studies have been conducted in the case of a double gate MOSFET to reduce the short channel effects such as using two channel materials or two gate metals [20][21][22]. However, a high-k materials have a disadvantage in that it is not superior to silicon dioxide in forming an interface with silicon used as a channel.…”

Section: Introductionmentioning

confidence: 99%

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Jung

2021

IJECE

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications

Cited by 26 publications

References 11 publications

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

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