Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect wires, and a greater impact of interconnect on total system performance. These changes have driven a considerable number of studies on single-net interconnect optimization, but relatively little work has been done to integrate the results on single-net optimization with the problem of global routing and interconnect optimization for the entire circuit. In this paper, we present the DECIMATE global router for performance driven standard cell design. The router applies both interconnect topology optimization and variable-width wire sizing optimization results to the global routing problem, while maintaining routing areas that are comparable with TimberWolf Systems' well-known commercial global router. Optimal selection of interconnection structures is shown to be an NP-Hard problem; we provide a simple heuristic for the problem, and show that it is e ective with experiments on industry benchmarks. Under the Elmore delay model, our global router produces as much as a 35 reduction in critical path delay o v er TimberWolf Systems' global router, while path length reductions are as large as 52. Circuit area optimization is performed taking into account v ariably-sized wires, xed routing topologies, and pre-existing obstacles; an improved cost function obtains as much as an 11.6 reduction in channel density o v er the result in 16 .