A genetic approach to test application time reduction for full scan and partial scan circuits

Rudnick, E.M.; Patel, J.H.

doi:10.1109/icvd.1995.512126

Cited by 20 publications

(5 citation statements)

References 18 publications

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“…Scan is performed only until all effective test bits are shifted to the right position and until all fault-affected response bits are shifted out. Reference [13] uses genetic algorithms to obtain compact test sets, which limit the scan operations. References [14] and [15] reduce test application time by generating a test for a sequential circuit using combinational test generation and sequential test generation adaptively.…”

Section: α = N Umber Of Transitions Per Clock Cycle (2)mentioning

confidence: 99%

Dynamic scan clock control for test time reduction maintaining peak power limit

Shanmugasundaram

Agrawal

2011

29th VLSI Test Symposium

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Abstract-We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The activity monitor is implemented either as on-chip hardware or through presimulated and stored test data. In either case a handshake protocol controls the rate of test data flow between the automatic test equipment (ATE) and device under test (DUT). The test time reduction accomplished depends upon an average activity factor α. For low α, about 50% test time reduction is analytically shown. With moderate activity, α = 0.5, simulated test data gives about 25% test time reduction for ITC02 benchmarks. For full scan s38584, the dynamic scan clock control reduced the test time by 19% when fully specified ATPG vectors were used and by 43% for vectors with don't cares. BIST with dynamic clock showed about 19% test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3% hardware overhead.

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Section: α = N Umber Of Transitions Per Clock Cycle (2)mentioning

confidence: 99%

Dynamic scan clock control for test time reduction maintaining peak power limit

Shanmugasundaram

Agrawal

2011

29th VLSI Test Symposium

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“…But this increases the number of scan-in and scan-out pins needed during test. Hybrid test generation techniques are introduced in [3], [4]. But, these techniques are computationally expensive and are not suitable for large sequential circuits.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Scan Tree Design for Compact Test Pattern Set

Banerjee

Chowdhury

Bhattacharya

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Various designs of scan paths based on tree-like structures have recently been suggested for reducing test application time or test data volume in today's high density VLSI circuits. However, these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set, and therefore, are unsuitable for highly compact test sets generated by efficient ATPG tools. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture. Given a compact test set, compatibility relationships among the flip-flops are first explored, and a graph-based heuristic algorithm is employed to construct a scan tree with minimal incompatibility. Next, the same combinational ATPG tool is rerun to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the structure of the scan tree. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing the total test application time significantly without any degradation of fault coverage.

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“…But this increases the number of scan-in and scan-out pins needed during test. Hybrid test generation techniques are introduced in [2,3]. But, these techniques are computationally expensive and are not suitable for large sequential circuits.…”

Section: Introductionmentioning

confidence: 99%

An efficient scan tree design for compact test pattern set

Banerjee

Chowdhury

Bhattacharya

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Various designs of scan paths based on tree-like structures have recently been suggested for reducing test application time or test data volume in today's high density VLSI circuits. Most of these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set, and therefore, are unsuitable for highly compact test sets generated by efficient ATPG tools. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture. Given a compact test set, compatibility relationships among the flip-flops are first explored, and a graph-based heuristic algorithm is employed to construct a scan tree with minimal incompatibility. Next, the same combinational ATPG tool is rerun to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the structure of the scan tree. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing the total test application time significantly without any degradation of fault coverage.

show abstract

A genetic approach to test application time reduction for full scan and partial scan circuits

Cited by 20 publications

References 18 publications

Dynamic scan clock control for test time reduction maintaining peak power limit

Dynamic scan clock control for test time reduction maintaining peak power limit

An Efficient Scan Tree Design for Compact Test Pattern Set

An efficient scan tree design for compact test pattern set

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