A general purpose multiple way partitioning algorithm

Yeh, Chingwei; Cheng, Chung‐Kuan; Lin, Tingting

doi:10.1145/127601.127706

Cited by 59 publications

(23 citation statements)

References 15 publications

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“…The most notable of them are the generalization of the FM algorithm for k-way partitioning [4,7], the spectral multi-way ratio-cut [6], the primal-dual algorithm of [5], the geometric embedding [9], the dual-net method [12], and the K-PMaLR algorithm [19]. A key problem faced by some of these algorithms is that the k-way FM re®nement algorithm easily gets trapped in local minima.…”

Section: Introductionmentioning

confidence: 99%

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Multilevel k-way hypergraph partitioning

Karypis

Kumar

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

230

272

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In this paper, we present a new multilevel k-way hypergraph partitioning algorithm that substantially outperforms the existing state-of-the-art K-PMaLR algorithm for multiway partitioning, both for optimizing local as well as global objectives. Experiments on the ISPD98 benchmark suite show that the partitionings produced by our scheme are on the average 15% to 23% better than those produced by the K-PMaLR algorithm, both in terms of the hyperedge cut as well as the (K À 1) metric. Furthermore, our algorithm is signi®cantly faster, requiring 4 to 5 times less time than that required by K-PMaLR.

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Section: Introductionmentioning

confidence: 99%

“…2 We were not able to compare results for 32-way partitioning, because they are not reported in [19]. FIGURE 5 The quality of the partitionings in terms of the cuts produced by hMETIS-Kway relative to those produced by K-PMaLR for an 8-and 16-way partitioning. Bars below the 1.0 line indicate that hMETIS-Kway performs better than K-PMaLR.…”

mentioning

confidence: 99%

Multilevel k-way hypergraph partitioning

Karypis

Kumar

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

230

272

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show abstract

“…The multi-way partitioning algorithms include the recursive bipartitioning by Kernighan and Lin [KeLi70], a generalization of the FM-algorithm with lookahead by Sanchis [Sa89], the primal-dual algorithm [YeCL91], and a generalization of the graph spectral-based partitioning method to multi-way ratio-cut by Chan, Schlag, and Zien [ChSZ93].…”

Section: Introductionmentioning

confidence: 99%

Multiway VLSI circuit partitioning based on dual net representation

Cong¹,

Labio²,

Shivakumar³

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propose a general paradigm for multi-way circuit partitioning based on dual net transformation. Given a netlist we first compute a K-way partitioning of nets based on the HDN representation, and then transform the K-way net partition into a K-way module partitioning solution. The main contribution of our work is in the formulation and solution of the K-way module contention (K-MC) problem, which determines the best assignment of the modules in contention to partitions while maintaining user-specified area requirements, when we transform the net partition into a module partition. Under a natural definition of binding factor between nets and modules, and preference function between partitions and modules, we show that the K-MC problem can be reduced to a min-cost max-flow problem. We present an efficient solution to the K-MC problem based on network flow computation.We apply our dual transformation paradigm to the well-known K-way FM partitioning algorithm (K-FM)

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“…Hierarchical information in the netlist, if present, is used to build the initial tree, which is then refined through the use of ratiocut partitioning [4]. Applying the approach of Yeh and Cheng [5], the tree guides the recursive partitioning of the circuit onto the Teramac network using min-cut partitioning algorithms [6,7]. The majority of compiler processing time is spent in this pass.…”

Section: Global Partitioningmentioning

confidence: 99%

Teramac-configurable custom computing

Amerson¹,

Carter²,

Culbertson³

et al.

Proceedings IEEE Symposium on FPGAs for Custom Computing Machines

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Abstract-The Teramac configurable hardware system can execute synchronous logic designs of up to one million gates at rates up to l megahertz. A fully configured Teramac includes half a gigabyte of RAM and hardware support for large multiported register files. The system has been built from custom FPGA's packaged in large multichip modules (MCMs). A large custom circuit (-1,000,000 gates) may be compiled onto the hardware in approximately 2 hours, without user intervention. The system is being used to explore the potential of custom computing machinery (CCM).

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A general purpose multiple way partitioning algorithm

Cited by 59 publications

References 15 publications

Multilevel k-way hypergraph partitioning

Multilevel k-way hypergraph partitioning

Multiway VLSI circuit partitioning based on dual net representation

Teramac-configurable custom computing

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