2003 8th International Symposium Plasma- And Process-Induced Damage.
DOI: 10.1109/ppid.2003.1199725
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A general concept for monitoring plasma induced charging damage

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Cited by 13 publications
(15 citation statements)
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“…• gate oxide leakage tests (in inversion and accumulation) [1][2][3], • threshold voltage characterisation (different methods) [1,3,7], • transconductance and drain-source current characterisation, • charge pumping [2,8,9], • constant current diagnostic stress [3,10] not intended to cause breakdown (in inversion and accumulation), • fast exponentially ramped current breakdown stress including soft breakdown detection [11] (in inversion and accumulation). All measurements were performed on an Agilent 4072 parametric test station with a fully automatic wafer prober except the charge pumping tests which were carried out on separate test equipment.…”
Section: Methodsmentioning
confidence: 99%
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“…• gate oxide leakage tests (in inversion and accumulation) [1][2][3], • threshold voltage characterisation (different methods) [1,3,7], • transconductance and drain-source current characterisation, • charge pumping [2,8,9], • constant current diagnostic stress [3,10] not intended to cause breakdown (in inversion and accumulation), • fast exponentially ramped current breakdown stress including soft breakdown detection [11] (in inversion and accumulation). All measurements were performed on an Agilent 4072 parametric test station with a fully automatic wafer prober except the charge pumping tests which were carried out on separate test equipment.…”
Section: Methodsmentioning
confidence: 99%
“…A first characterisation measurement for any PID assessment is a gate oxide leakage current test of the investigated MOS transistor [1][2][3]10,12]. A high initial leakage current is a strong indicator for a dramatic PID degradation.…”
Section: Gate Oxide Leakage Currentsmentioning
confidence: 99%
“…The fast Wafer Level Reliability (fWLR [6]) characterisation of the MOS transistors consisted of three parts as reported in [7]. All MOS transistors were measured for their initial transistor parameters.…”
Section: Experimental: Stress + Measurementsmentioning
confidence: 99%
“…Due to plasma induced charging of the dielectric layer the lifetime can be significantly reduced [35][36][37]. In most cases PID cannot be completely ruled out from very early processing steps, such as polysilicon etch or contact hole etch, even when the dielectric test structure is protected by diodes connecting gate to bulk.…”
Section: Trouble Shootingmentioning
confidence: 99%