A general approach for identifying hierarchical symmetry constraints for analog circuit layout

Kunal, Kishor; Poojary, Jitesh; Dhar, Tonmoy; Madhusudan, Meghna; Harjani, Ramesh; Sapatnekar, Sachin S.

doi:10.1145/3400302.3415685

Cited by 24 publications

(4 citation statements)

References 22 publications

(20 reference statements)

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“…Wu et al [87] further extend the graph representation by embedding pin connection information into edge weights and generate constraints based on subgraph isomorphism with a template circuit library. Eick et al [88] directly generate constraints by pattern matching and group constraints hierarchically based on structural signal flow graphs.…”

Section: Automatic Constraint Generationmentioning

confidence: 99%

Challenges and opportunities toward fully automated analog layout design

et al. 2020

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Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

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Section: Automatic Constraint Generationmentioning

confidence: 99%

Challenges and opportunities toward fully automated analog layout design

et al. 2020

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“…These constraints are extracted naturally as part of auto-annotation. In contrast with prior methods that are based on simulation-intensive sensitivity analysis [16] or graph traversal based exact matching to templates [4], the approach in ALIGN method [9] combines graph traversal methods with machine learning based methods and is computationally efficient, capable of finding hierarchically nested symmetry constraints even under approximate matches. Electrical constraints: ALIGN generates a layout based on a fixed netlist, and performance shifts are driven by changes in parasitics from netlist-level estimates to post-layout values.…”

Section: Constraint Generationmentioning

confidence: 99%

ALIGN: A System for Automating Analog Layout

Dhar¹,

Kunal²,

Li³

et al. 2020

Preprint

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ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits.

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“…Liu et al [ 12 ] initially proposed a fast symmetric constraint detection method based on graph matching; however, this method has limited robustness and is only applicable to specific circuit structures. This work was further extended in work [ 13 ] using graph neural networks, which enable rapid retrieval of subgraphs with similar structures, thereby enhancing the algorithm’s generality. Subsequently, Kunal et al introduced a graph convolutional neural network called GANA (graph convolutional network-based automated netlist annotation for analog circuits) [ 14 ] for identifying subcircuits.…”

Section: Introductionmentioning

confidence: 99%

Parsing Netlists of Integrated Circuits from Images via Graph Attention Network

Hu,

Zhan,

Tong

2023

Sensors

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A massive number of paper documents that include important information such as circuit schematics can be converted into digital documents by optical sensors like scanners or digital cameras. However, extracting the netlists of analog circuits from digital documents is an exceptionally challenging task. This process aids enterprises in digitizing paper-based circuit diagrams, enabling the reuse of analog circuit designs and the automatic generation of datasets required for intelligent design models in this domain. This paper introduces a bottom-up graph encoding model aimed at automatically parsing the circuit topology of analog integrated circuits from images. The model comprises an improved electronic component detection network based on the Swin Transformer, an algorithm for component port localization, and a graph encoding model. The objective of the detection network is to accurately identify component positions and types, followed by automatic dataset generation through port localization, and finally, utilizing the graph encoding model to predict potential connections between circuit components. To validate the model’s performance, we annotated an electronic component detection dataset and a circuit diagram dataset, comprising 1200 and 3552 training samples, respectively. Detailed experimentation results demonstrate the superiority of our proposed enhanced algorithm over comparative algorithms across custom and public datasets. Furthermore, our proposed port localization algorithm significantly accelerates the annotation speed of circuit diagram datasets.

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A general approach for identifying hierarchical symmetry constraints for analog circuit layout

Cited by 24 publications

References 22 publications

Challenges and opportunities toward fully automated analog layout design

Challenges and opportunities toward fully automated analog layout design

ALIGN: A System for Automating Analog Layout

Parsing Netlists of Integrated Circuits from Images via Graph Attention Network

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