A general analysis on the timing jitter in D/A converters

Doris, Kostas; Roermund, Arthur van; Leenaerts, D.M.W.

doi:10.1109/iscas.2002.1009791

Cited by 27 publications

(13 citation statements)

References 10 publications

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“…This requires fast transitions on the signals controlling the switches [16]. Fourth, the sampling clock jitter results in the variation in the sample time from cycle-to-cycle that introduces distortion [19] [20]. Lastly, an IR drop along the DAC supply lines causes a variation in the gate-to source voltage of the current source leading to DNL errors in the DAC [16].…”

Section: Characteristics Of Nyquist Dacsmentioning

confidence: 99%

“…This results in distortion components in Nyquist DACs, but in ∆Σ DACs it results in the folding of the high frequency noise resulting in a reduction of SNDR. Some analysis of the jitter effects has been earlier performed in [19] and [20].…”

Section: Choice Of Multiplexing Strategymentioning

confidence: 99%

“…The effect of DCE on TIDSM DACs has received very less attention in the literature. Previous works [19,20] have focused only on the analysis of sampling time errors in non-interleaved Nyquist and ∆Σ DACs resulting from stochastic clock jitter, which is not applicable in the case of a deterministic error like the DCE. In [67], the effect of time-average frequency (TAF) and flying-adder (FA) clocks on noninterleaved Nyquist DACs has been studied and a closed-form expression for the SDR is presented.…”

Section: Effect Of Clock Duty Cyclementioning

confidence: 99%

See 2 more Smart Citations

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: Characteristics Of Nyquist Dacsmentioning

confidence: 99%

Section: Choice Of Multiplexing Strategymentioning

confidence: 99%

Section: Effect Of Clock Duty Cyclementioning

confidence: 99%

See 1 more Smart Citation

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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“…Assuming jitter in the picoseconds range, this is a good approximation up to many MHz and in oversampled DACs it's a reasonable and common approach [33]. The error waveform is now approximated as Dirac-pulses with weight given by the real pulse area AÁJ, called error area modelling.…”

Section: Jitter Error Modelling Reviewmentioning

confidence: 99%

Review and advances in delta-sigma DAC error estimation based on additive noise modelling

Løkken

Vinje

Hernes

et al. 2009

Analog Integr Circ Sig Process

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High-resolution and very high resolution data conversion is dominated by the use of delta-sigma modulating converters. Oversampling and noise-shaping is employed to enable a coarsely quantized conversion with high effective resolution. The time-domain output waveform from a delta-sigma modulator is often impossible to predict analytically, therefore modulator design is largely based on high level digital simulations and rule-of-thumb estimation. However, the output waveform also largely determines the distortion caused by analog error sources in the converter. Therefore optimization of the modulator with regards to digital quantization noise might not yield an optimal design when analog errors are included. This paper extends common estimation methods to include analog error sources, with the objective of enabling more global rule-of-thumb optimization.

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“…The effect of DCE on TIDSM DACs has received very less attention in the literature. Previous works [8], [9] have focused only on the analysis of sampling time errors in non-interleaved Nyquist and ∆Σ DACs resulting from stochastic clock jitter, which is not applicable in the case of a deterministic error like the DCE. In [10], the effect of time-average frequency (TAF) and flying-adder (FA) clocks on non-interleaved Nyquist DACs has been studied and a closed-form expression for the SDR is presented.…”

Section: Introductionmentioning

confidence: 99%

Effect of Clock Duty-Cycle Error on Two-Channel Interleaved <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math></inline-formula> DACs

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Ojani

Alvandpour

2015

IEEE Trans. Circuits Syst. II

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Abstract-Time-interleaved ∆Σ (TIDSM) DACs have the potential for a wideband operation. The performance of a twochannel interleaved ∆Σ DAC is very sensitive to the duty-cycle of the half-rate clock. This paper presents a closed-form expression for the SNDR loss of such DACs due to duty cycle error for modulators with a noise transfer function of (1 − z −1 ) n . Adding a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved ∆Σ DAC in the early stage of the design process.

show abstract

A general analysis on the timing jitter in D/A converters

Cited by 27 publications

References 10 publications

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Review and advances in delta-sigma DAC error estimation based on additive noise modelling

Effect of Clock Duty-Cycle Error on Two-Channel Interleaved <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math></inline-formula> DACs

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