Effect of Clock Duty-Cycle Error on Two-Channel Interleaved &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$&lt;/tex-math&gt;&lt;/inline-formula&gt; DACs

All-digital radio-over-fiber (RoF) transmission has attracted a significant amount of interest in digital-centric systems or centralized networks because it greatly simplifies the front-end hardware by using digital processing. The sigma-delta modulator (SDM)-based all-digital RoF approach pushes the digital signal processing as far as possible into the transmit chain. We present a real-time 100-GS/s fourth-order single-bit SDM for all-digital RoF transmission in the high-frequency band without the aid of analog/optical up-conversion. This is the fastest sigma-delta modulator reported and this is also the first real-time demonstration of sigma-delta-modulated RoF in the frequency band above 24 GHz. 4.68 Gb/s (2.34 Gb/s) 64-QAM is transported over 10-km standard single-mode fiber in the C-band with 6.46% (4.73%) error vector magnitude and 3.13 Gb/s 256-QAM can be even received in an optical back-to-back configuration. The carrier frequency can be digitally tuned at run-time, covering a wide frequency range from 22.75 to 27.5 GHz. Besides, this high-speed sigma-delta modulator introduces less than 1 µs latency in the transmit chain. Its all-digital nature enables network virtualization, making the transmitter compatible with different existing standards. The prominent performance corroborates the strong competitiveness of this SDMbased RoF approach in high-frequency RoF 5G communication.

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An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

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Alvandpour

2015

IEEE J. Solid-State Circuits

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This work presents an 11 GS/s 1.1 GHz bandwidth interleaved ∆Σ DAC in 65 nm CMOS for the 60-GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output resulting in a predominantly digital DAC with only fifteen analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the ∆Σ DAC achieves a 53 dB SFDR, −49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed ∆Σ DAC can satisfy the spectral mask of the IEEE 802.11ad WiGig standard with a second order reconstruction filter.

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Effect of Clock Duty-Cycle Error on Two-Channel Interleaved <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math></inline-formula> DACs

Cited by 5 publications

References 11 publications

Duty Cycle Distortion in Half-rate Nyquist DACs with Limited Output Bandwidth

Duty Cycle Distortion in Half-rate Nyquist DACs with Limited Output Bandwidth

Real-Time 100-GS/s Sigma-Delta Modulator for All-Digital Radio-Over-Fiber Transmission

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS

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