A general algorithm for tiling the register level

Abstract

Tiling is a well-known loop transformation that can be used to exploit data reuse at the register level and to improve a program's ILP. Previous work on tiling and also commercial compilers are able to perform tiling for the register level in more than one dimension when the iteration space is rectangular. However, they either cannot handle or can only handle limited cases of non-rectangular iteration spaces. Nonrectangular iteration spaces 1 are commonly found in linear algebra algorithms or can arise as a result of applying previous transformations such as loop skewing. In this paper we present a new general algorithm to perform tiling for the register level in more than one dimension in both rectangular and nonrectangular iteration spaces. Our method uses index set splitting to distinguish loop nests that traverse boundary tiles of the tiled iteration space from loop nests that traverse nonboundary tiles. We evaluate our method using as benchmarks typical linear algebra algorithms having non-rectangular iteration spaces. Results measured on both ALPHA 21064 and MIPS R10000 machines show that our method achieves speedups in the range of 1.11 to 5.96 over commercial compilers and preprocessors able to perform optimizing code transformations. INTRODUCTIONModern processors issue multiple instructions per cycle to exploit instruction level parallelism (ILP) and use several memory levels to reduce the average memory access time. To achieve high performance in these processors, the compilers have to be able to exhibit a program's ILP and to increase data locality to take full advantage of the architecture and to minimize the data movement between different levels of the memory hierarchy. Being able to exploit data reuse at the register level is extremely important in today's superscalar microprocessors, since the register level directly feeds the processor functional units and, if the register level is not properly exploited, then the number of first level cache ports bounds processor performance. Much research has been devoted to exploit data reuse at the cache level 1 We refer as a "non-rectangular" iteration space to an iteration space defined by loops whose bounds are compositions (max or min) of affine functions of the surrounding loops iteration variables. This includes iteration spaces whose bounds are not parallel to the iteration space axes. [19], and also commercial compilers and preprocessors, either cannot handle or can only handle limited cases of non-rectangular iteration spaces. Tiling arbitrary nonrectangular iteration spaces is not generally considered because it is not trivial [19]. We note that unroll & jam can be applied in multiple dimensions and, in rectangular iteration spaces, it is the same transformation as register tiling. However, unroll & jam can only be applied to limited cases of non-rectangular spaces [2].In this paper we present a new general method to perform tiling for the register level that blocks in several dimensions of the iteration space, improving the performance of...

On the performance of hand vs. automatically optimized numerical codes

“…In particular, he only allows one inner loop to have bounds that are affine function of only one iteration variable of tiled loops. Our previous work [14] extends that of [4] [5] by allowing several loops to have affine bounds of multiple tiled loops iteration variables. Moreover, he does not compare their performance results to hand-optimized codes.…”

“…In previous work [13] [14][15], we proposed a compiler technique able to automatically optimize numerical codes that define non-rectangular iteration spaces. In this paper we want to show that this compiler technique can rival hand-optimized codes.…”

“…In non-rectangular loop nests, the action of fully unrolling the loops is far from being trivial due to the irregular nature of the iteration space. In [14], we proposed a compiler algorithm to perform tiling at the register level that handles arbitrary iteration space shapes (and not only simple rectangular shapes) and we showed it to be effective [12].…”

“…Now, when multilevel tiling includes the register level, another difficulty appears. The complexity and the amount of code (number of loop nests) generated by our register tiling technique [14] both depend on the number of bounds of the loops that have to be fully unrolled (the innermost loops after multilevel tiling). Therefore, it is critical to compute exact bounds 1 and avoid the generation of redundant bounds 2 .…”

“…When the iteration space is non-rectangular, the bounds of the element loops do not determine a constant number of iterations and, consequently, it is not possible to directly fully unroll those loops. In [14][15] we show how index set splitting [25] can be used repeatedly to divide the tiled iteration space into partitions, such that, in each of these partitions the maximum number of loops that provide data reuse at the register level (element loops) can be fully unrolled. The idea consists on taking the loop nest resulting from the iteration space tiling phase and breaking it into several loop nests (partitions), one of which will traverse all (and only) core-tiles while the remaining loop nests will traverse the different types of boundary-tiles.…”