A GaAs Based Metal-Interlayer- Semiconductor S/D Finfet

Sadasivan, Saranya T; Khan, T. E. Ayoob; Hameed, Shahul

doi:10.1109/icetietr.2018.8529122

Cited by 1 publication

(1 citation statement)

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“…FinFET, one of the sub nano multi-gated gadgets [21], is regarded the best technology to extend CMOS downscaling to the sub-10 nm regime [22]. Predominant scalability [23], minimal gate leakage current [24], magnificent control of SCEs to guarantee higher short channel accomplishments, relative immunisation to the gate line-edge roughness [25], being compatible with the current technologies and most importantly better gate control are the key properties of these device [26,27,28,29,30,31]. Earlier studies showed that the fin dimensions are very critical when generating the enhanced drive current along with threshold voltage (V T H ) [32][33] hence performance can be improved by varying the geometries of the fin while watching out for any trade-offs in current and threshold voltage [34].…”

Section: Introductionmentioning

confidence: 99%

Design of a 30 nm Germanium FinFET by Parameter Optimization

Mogosetso

Lebekwe

Ditshego

2022

AEF

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Germanium (Ge) is envisioned as a suitable channel candidate for field-effect transistors (FET). Properties of Ge such as high carrier mobility, compatibility with Si and adaptability with high-k materials makes it comparable to silicon. This paper presents a detailed design of a 30 nm Ge based FinFET by parameter optimization using Silvaco software. Poisson and Schrodinger equation is used to come up with an analytical quantum model. The quantum model is developed based on theory of a double gate (DG) FET but the final design is a trigate (TG) device since they are more scalable. The quantum attributes of DG MOSFET are acquired by adopting the coupled Poisson–Schrodinger equation with the aid of the variational approach. The ratio of channel length (LC) to fin height (Hfin) to fin thickness (tfin) is 4:2:1. The channel length is taken as the gate length (LG) although they are slightly differ mathematically due to side diffusion of the implanted ions. Simulation results show that physical parameters such as dimensions influence electrical characteristics of the device such as threshold voltage (VTH). Much focus is on optimization of the on/off current ratio (ION/OFF) and VTH performances. ION/OFF≈ 106 is achieved at carrier concentration in the range 1 × 1018≤ nd≤ 1.22 × 1018 and in this scenario, VTH = 0.4V . Systematical investigation is presented using IV characteristics to demonstrate the sensitivity or how critical design parameters of Ge FinFET are to the device’s figure of merits. Device performs well at low voltages but breaks down at higher drain voltages (VDS≥ 4V). Gate source voltages (VGS) range between 0.05V≤ VGS ≤ 1V and conductance is dependent on it. Effects of DIBL, which is around 0.031, and velocity saturation are studied to determine how they can be suppressed during the design process.

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