A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

Craninckx, Jan; Liu, M.; Hauspie, D.; Giannini, Vito; Kim, T.; Lee, J.; Libois, Michael; Debaillie, D.; Soens, Charlotte; lngels, M.; Baschirotto, A.; Driessche, Joris Van; Perre, Liesbet Van der; Vanbekbergen, Peter

doi:10.1109/isscc.2007.373436

Cited by 66 publications

(27 citation statements)

References 7 publications

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“…Source-followers buffering the IFoutputs plus bias circuitry consume 13mW. The power consumption of the core circuit is 16mW from a 1.2V supply.The achieved performance compares favorably to the state-of-theart [1][2][3], especially with respect to RF bandwidth and linearity (see Fig. 17.3.6).…”

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confidence: 79%

“…17.3.7. The core measures less than 0.01mm 2 . Measurements are performed on packaged PCB-mounted samples.…”

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confidence: 92%

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confidence: 99%

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A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS

Blaakmeer

Klumperink

Leenaerts

et al. 2008

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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Wideband receivers are required for many applications including the upcoming software-defined radio (SDR) architectures and ultra-wideband communication standards [1][2][3]. These standards cover a frequency spectrum from a few hundred MHz up to 6GHz. Co-operability with other communication devices (e.g., cellular and WLAN) operating in the same spectrum is mandatory, setting especially stringent demands on the wideband linearity of such receivers. The use of area-consuming on-chip inductors must be avoided as the cost per area of modern CMOS processes is high. The receiver preferably has a single-ended RF-input, as this avoids the use of an external broadband balun and its accompanying losses. A 65nm CMOS inductor-less wideband LNAmixer topology is presented, merging a current commutating I/Qmixer with a noise canceling balun-LNA. Figure 17.3.1 shows the topology of the proposed receiver frontend, which combines the functionality of a balun, an LNA and an I/Q-Mixer (Blixer) into one circuit cell. The transistor in commongate (CG) configuration gives wideband input matching (Z in ≈1/g m ). The inverter-based common-source (CS) stage produces a current in anti-phase with the CG output current, providing the single-to-differential conversion. The normally dominant thermal noise of the CG stage is canceled robustly [4]. The noise current of the CG transistor generates a noisy input voltage on the source resistance (R S ). This voltage results in an output current in the CS stage which is in-phase and fully correlated with the noise current of the CG transistor. The CG noise can thus be canceled at the differential output. The effective g m of the CS stage is 4 times higher than the CG g m in order to limit its noise contribution. The output currents of the CG and CS stage (g m ·v rf and 4·g m ·v rf in Fig. 17.3.1) are distributed to two identical current-commutating mixer cells, as shown in Fig. 17.3.2. The drains of the transistors commutating the CS current are loaded by only ¼ of the total RC load. The difference in loading compensates the (4×) difference in g m of the CG and CS stage, leading to equal conversion gain of the CG and CS side of the circuit. This gain balancing renders simultaneous canceling of the noise and distortion of the CG transistor, as in the LNA in [5]. However, in contrast to that design, here the canceling takes place at the IF output, after frequency translation. As the distortion of the CG transistor is canceled, the inverter-based CS stage is biased for minimal 2 ndorder distortion to obtain a high IIP2 of the complete circuit. In contrast to narrowband systems 2 nd -order distortion products can fall in-band, thus obtaining a high IIP2 is important for wideband receivers. The Blixer topology has only two internal RF nodes, the drains of the CG and CS transistors. The impedance at these points is set by the input impedance of the mixer devices. This impedance (~1/g m of the mixer transistors) is low, approximately 100Ω and 25Ω for the CG and CS side, respectively. The absence of high ...

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confidence: 79%

“…17.3.7. The core measures less than 0.01mm 2 . Measurements are performed on packaged PCB-mounted samples.…”

mentioning

confidence: 92%

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A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS

Blaakmeer

Klumperink

Leenaerts

et al. 2008

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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“…Delay-locked loop (DLL)-based multipliers can provide both functions. Two recently reported SDR transceivers use this method [34,35]. DLL-based multipliers take the multiple phase copies from a tapped delay line and process them, typically with combination logic, to construct an output signal at some multiple of the input reference frequency.…”

Section: Frequency Extensionmentioning

confidence: 99%

Software‐Defined Transceivers

Cafaro

Stengel

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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“…Software-defined and cognitive radio receivers use direct-conversion or zero-IF architecture [9,18]. Figure 1 shows a typical block diagram for an integrated wireless receiver using the zero-IF architecture.…”

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confidence: 99%

Multistandard Analogue Baseband Filters for Software-Defined and Cognitive Radio Receivers

Sun

Moritz

Zhu

2011

Circuits Syst Signal Process

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Analogue baseband filters are an important circuit for channel select and anti-aliasing in wireless and mobile communication systems. For software and cognitive radio, they must be widely tunable and reconfigurable to accommodate existing, emerging, and future wireless and mobile standards. In this paper, design considerations of tunable and programmable filters for highly integrated multistandard receivers are presented. General background of multistandard integrated receivers and design challenges of analogue baseband filters are given. Circuit techniques for baseband filter design including the widely used active-RC and Gm-C circuits are described. Filter structures and design methods for high-order baseband filters are reviewed. On-chip tuning issues and methods are discussed. Results and performances of some published design examples are summarized. Future directions are also pointed out.

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A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

Cited by 66 publications

References 7 publications

A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS

A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS

Software‐Defined Transceivers

Multistandard Analogue Baseband Filters for Software-Defined and Cognitive Radio Receivers

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