2022
DOI: 10.3390/electronics11152465
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A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design

Abstract: Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level i… Show more

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Cited by 3 publications
(2 citation statements)
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References 15 publications
(73 reference statements)
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“…The proposed RB-LDNUR D-latch, DICE [20], DNCS SEU tolerant latch [7], DNUCT [21], NTHLTCH [10], TPDICE-based latch [17], LSEDUT latch [12], DNURHL [19], RDTL [17], RH-latch [22], FPADRL [23], LOCDNUTRL [24], HTNURE [25], LOCTNUTRL [24] are simulated at 0.8 V at room temperature using Synopsys ® HSPICE in 22nm CMOS technology from PTM library [26]. For a fair comparison, PMOS transistors have an aspect ratio of W/L = 35 nm/22 nm, and NMOS transistors have an aspect ratio of W/L = 24 nm/22 nm.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…The proposed RB-LDNUR D-latch, DICE [20], DNCS SEU tolerant latch [7], DNUCT [21], NTHLTCH [10], TPDICE-based latch [17], LSEDUT latch [12], DNURHL [19], RDTL [17], RH-latch [22], FPADRL [23], LOCDNUTRL [24], HTNURE [25], LOCTNUTRL [24] are simulated at 0.8 V at room temperature using Synopsys ® HSPICE in 22nm CMOS technology from PTM library [26]. For a fair comparison, PMOS transistors have an aspect ratio of W/L = 35 nm/22 nm, and NMOS transistors have an aspect ratio of W/L = 24 nm/22 nm.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…In [2], the authors present a cell-level radiation-hardening-by-design (RHBD) method based on commercial processes, showcasing new radiation-hardened D-type flip-flops (DFF) with highly improved SEU tolerance compared to standard DICE flip-flops even with TMR. Article [3] presents a fully polarity-aware double-node-upset (DNU)-resilient latch. The circuit boasts multiple thresholds, an increased number of SEU-insensitive nodes, low power dissipation, and has the strongest radiation-hardening capability among other DNU-resilient latches.…”
mentioning
confidence: 99%