A Fully Integrated UWB PHY in 0.13/spl mu/m CMOS

Aytur, T.; Kang, Han-Chang; Mahadevappa, R.; Altıntas, Mert; Brink, Stephan ten; Diep, Thanh; Hsu, Ching-Ting; Feng, Shi; Yang, Fei; Lee, Chao-Cheng; Yan, Ran; Razavi, Behzad

doi:10.1109/isscc.2006.1696073

Cited by 13 publications

(7 citation statements)

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“…Additionally, we compare the chip area of SC-UWB with that of the published system-level MB-OFDM chips [12] [13], as shown in Table V. The areas of the three chips are equivalently converted into the case of 65nm CMOS for a fair comparison.…”

Section: Experimental Results and The Sc-uwb Chipmentioning

confidence: 99%

SC-UWB: A low-complexity UWB technology for portable devices

Xiao

Pei

et al. 2011

2011 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

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Ultra Wideband (UWB) technology has attracted widespread attention all over the world because of potential applications in high-rate short-range communications. The existing UWB technologies, e.g., the direct-sequence UWB (DS-UWB) and the multi-band orthogonal frequency division multiplexing (MB-OFDM), have high complexity, which results in high power consumption and cost, and limits its marketing. In this paper we propose and introduce a single carrier UWB (SC-UWB) technology based on a deep investigation of the existing UWB technologies. The proposed SC-UWB technology has much lower complexity, and aims at low-power portable applications. Also, we show some experimental results on the SC-UWB technology and present the fabricated SC-UWB chip. The measured results show that the SC-UWB can achieve good performance in a practical office environment, and the die size can be reduced by about 41.88% compared to that of the published MB-OFDM chips.

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Section: Experimental Results and The Sc-uwb Chipmentioning

confidence: 99%

SC-UWB: A low-complexity UWB technology for portable devices

Xiao

Pei

et al. 2011

2011 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

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“…Figure 8.1 demonstrates the proposed architecture of the fast hopping injection-locked synthesizer which targets WiMedia UWB communication in bandgroup 1. The synthesizer consists of a CP DLL that is locked to a 528-MHz reference clock, and according to the number of delay elements in the VCDL (N=13, 15,17), it generates equally-spaced output phases. The DLL phases are then converted into currents through V-I converters in the EC.…”

Section: Architecturementioning

confidence: 99%

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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“…Noncoherent detection schemes tend to be lower power. Adapted from ref [27,[28][29][30][31][32][33] for 80-85 in the figure and [34][35][36][37][38][39] for 106-111 in the figure Fig. 3.33 Schematic of non-coherent detection scheme Short transient decay times allow the receiver to be duty cycled to less than 0.1 % (10 ns in a 10 us period), yielding an average power consumption of ~ 12 µW in our 90 nm CMOS example, including leakage.…”

Section: Peak-detection Based Self-timed Pulse-detectionmentioning

confidence: 99%