A fully integrated multi-CPU, GPU and memory controller 32nm processor

Yuffe, Marcelo; Knoll, Ernest; Mehalel, Moty; Shor, Joseph; Kurts, Tsvika

doi:10.1109/isscc.2011.5746311

Cited by 80 publications

(37 citation statements)

References 5 publications

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“…The prototype query was executed on a quad-core 2.2 GHz processor using the Sandy Bridge architecture [32]. To simplify the calculation, the query process was bound to a single CPU core.…”

Section: Methodsmentioning

confidence: 99%

A framework for cloud-based context-aware information services for citizens in smart cities

2014

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Background: In the context of smart cities, public participation and citizen science are key ingredients for informed and intelligent planning decisions and policy-making. However, citizens face a practical challenge in formulating coherent information sets from the large volumes of data available to them. These large data volumes materialise due to the increased utilisation of information and communication technologies in urban settings and local authorities' reliance on such technologies to govern urban settlements efficiently. To encourage effective public participation in urban governance of smart cities, the public needs to be facilitated with the right contextual information about the characteristics and processes of their urban surroundings in order to contribute to the aspects of urban governance that affect them such as socio-economic activities, quality of life, citizens well-being etc. The cities on the other hand face challenges in terms of crowd sourcing with quality data collection and standardisation, services inter-operability, provisioning of computational and data storage infrastructure. Focus: In this paper, we highlight the issues that give rise to these multi-faceted challenges for citizens and public administrations of smart cities, identify the artefacts and stakeholders involved at both ends of the spectrum (data/service producers and consumers) and propose a conceptual framework to address these challenges. Based upon this conceptual framework, we present a Cloud-based architecture for context-aware citizen services for smart cities and discuss the components of the architecture through a common smart city scenario. A proof of concept implementation of the proposed architecture is also presented and evaluated. The results show the effectiveness of the cloud-based infrastructure for the development of a contextual service for citizens.

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“…The prototype query was executed on a quad-core 2.2 GHz processor using the Sandy Bridge architecture [32]. To simplify the calculation, the query process was bound to a single CPU core.…”

Section: Methodsmentioning

confidence: 99%

A framework for cloud-based context-aware information services for citizens in smart cities

2014

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“…Although the figure shows a unidirectional, it is a stack shift direction, and a bidirectional path is possible using the proposed dynamic CSD architecture. By applying the dynamic CSD and a modular structure that does not require a large number of metal wire layers, the folded linear network can be placed on the higher metal layers in a fashion similar to that of a recent many-core processor [8]. The S-topology network supports the ability to unchain (split) the array into any arbitrary shape that may be formed by connecting the clusters as shown in Figure 5.…”

Section: S-topologymentioning

confidence: 99%

Very Large-Scale Integrated Processor

Takano

2013

IJNC

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In the near future, improvements in semiconductor technology will allow thousands of resources to be implementable on chip. However, a limitation remains for both single large-scale processors and many-core processors. For single processors, this limitation arises from their design complexity, and regarding the many-core processors, an application is partitioned to several tasks and these partitioned tasks are mapped onto the cores. In this article, we propose a dynamic chip multiprocessor (CMP) model that consists of simple modules (realizing a low design complexity) and does not require the application partitioning since the scale of the processor is dynamically variable, looking like up or down scale on demand. This model is based on prior work on adaptive processors that can gather and release resources on chip to dynamically form a processor. The adaptive processor takes a linear topology that realizes a locality based placement and replacement using processing elements themselves through a stack shift of information on the linear topology of the processing element array. Therefore, for the scaling of the processor, a linear topology of the interconnection network has to support the stack shift before and after the up-or down-scaling. Therefore, we propose an interconnection network architecture called a dynamic channel segmentation distribution (dynamic CSD) network. In addition the linear topology must be folded on-chip into two-dimensional plane. We also propose a new conceptual topology and its cluster which is a unit of the new topology and is replicated on the chip. We analyzed the cost in terms of the available number of clusters (adaptive processors with a minimum scale) and delay in Manhattan-distance of the chip, as well as its peak Giga-Operations per Second (GOPS) across the process technology scaling.

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“…We base that prediction on the following observations: the recently announced 28 nm Xilinx Virtex-7 FPGA family offer 1.78 times more DSP48E1 blocks compared to Virtex-6, and also some marginal increase in clock frequency (we do not consider other FPGA manufacturers, such as Altera and Lattice, as they do not offer devices of such size). At the same time, 32 nm Intel Sandy Bridge processor offer the vector instruction set (AVX) two times wider than the previous SSE, and also better performance per core compared to the previous generation of processors [19]. There is currently up to 8 cores per chip (in Intel processors), and this number will probably significantly increase in the future [20].…”

Section: Multiplicationmentioning

confidence: 99%

FPGA accelerator for floating-point matrix multiplication

Jovanovic

Milutinović

2012

IET Comput. Digit. Tech.

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Abstract:This study treats architecture and implementation of a FPGA accelerator for double-precision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering, and simplifies placement and routing on the chip. The authors show that such architecture is especially well suited for full-duplex communication links between the accelerator and the host processor. The architecture requires the result blocks to be accumulated by the host processor; however, the authors show that typically more than 99% of all arithmetic operations are performed by the accelerator. The implementation focuses on efficient use of embedded FPGA resources, in order to allow for a large number of processing elements (PEs). Each PE uses 8 Virtex-6 DSP blocks. Both adders and multipliers are deeply pipelined and use several FPGA-specific techniques to achieve small area size and high clock frequency. Finally, the authors quantify the performance of accelerator implemented in Xilinx Virtex-6 FPGA, with 252 PEs running at 403 MHz (achieving 203.1 GFLOPS), by comparing it to DGEMM function from MKL, ACML, GotoBLAS and ATLAS libraries executing on Intel Core2Quad and AMD Phenom X4 microprocessors running at 2.8 GHz. The accelerator performs 4.5 times faster than the fastest processor/library pair.

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A fully integrated multi-CPU, GPU and memory controller 32nm processor

Cited by 80 publications

References 5 publications

A framework for cloud-based context-aware information services for citizens in smart cities

A framework for cloud-based context-aware information services for citizens in smart cities

Very Large-Scale Integrated Processor

FPGA accelerator for floating-point matrix multiplication

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