A Fully Integrated High Efficiency RF Power Amplifier for WLAN Application in 40 nm Standard CMOS Process

Ryu, Nam-Sik; Park, Bonghyuk; Jeong, Yongchae

doi:10.1109/lmwc.2015.2421351

Cited by 24 publications

(12 citation statements)

References 5 publications

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“…However, recently, CMOS power amplifiers are under vigorously study in hopes of reducing the overall unit cost of production of RF systems [7][8][9][10][11][12][13][14]. One of the many advantages of the CMOS power amplifier is that it can be integrated with digital control blocks and analog circuits to complete a fully integrated SoC [15,16].…”

Section: Introductionmentioning

confidence: 99%

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

Son¹,

Yoo²,

Lee³

et al. 2019

PIER C

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In this work, we propose a balun embedded driver stage to enhance the bandwidth and minimize the chip size of a differential CMOS power amplifier. By removing the passive input transformer, the bandwidth and chip size are improved. The proposed driver stage acts as an input balun as well as the driver stage for the power stage. The proposed driver is composed of a cascade connected PMOS, an inductor, and NMOS to generate the differential output signal. For the function of the input balun, the gate of the PMOS is connected to the drain of the NMOS. To verify the feasibility of the proposed balun embedded driver stage, we design a differential CMOS power amplifier for 5-GHz IEEE 802.11n WLAN applications. The designed power amplifier is fabricated using the 180-nm SOI RF CMOS process. The measured 3-dB bandwidth is approximately 2.5 GHz. The chip size of the fully integrated power amplifier, including input and output matching networks and test pads, is 0.885 mm 2. The measured maximum output power is 20.18 dBm with a PAE of 10.16%.

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Section: Introductionmentioning

confidence: 99%

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

Son¹,

Yoo²,

Lee³

et al. 2019

PIER C

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show abstract

“…Unfortunately, the problem becomes more severe in CMOS process, which has a low break down voltage of the transistor and lossy silicon substrate . The performance of the PA is critical to the overall system, so research on PAs continues and many designs for PAs in the CMOS process are still being reported and confirm their feasibility …”

Section: Introductionmentioning

confidence: 99%

“…5 The performance of the PA is critical to the overall system, so research on PAs continues and many designs for PAs in the CMOS process are still being reported and confirm their feasibility. [6][7][8][9] One solution for enhancing PA performance is a power combining technique. [10][11][12][13][14][15] Besides increasing the output power, this technique has the additional advantage of allowing multi-mode operation by turning off one side stage.…”

mentioning

confidence: 99%

A study comparing current and voltage combining techniques for CMOS power amplifiers for WLAN applications

Park

Lee

Park

2019

Micro & Optical Tech Letters

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This article presents CMOS power amplifiers for WLAN applications. These power amplifiers use current and voltage combining techniques for simultaneous improvement of the output power and efficiency, respectively, and are analyzed to determine which technique is more suitable for WLAN applications. The power amplifiers are fabricated with a 180 nm CMOS process. Their performance is verified using an 802.11 g modulated signal with 64 QAM, 20 MHz of bandwidth, and 54‐Mbps at 2.7 GHz. The measurements of the current and voltage combining power amplifiers show about 21.9 and 21.8 dBm of average output power, respectively, at −25 dB error vector magnitude (EVM), and about 20.2 and 18 dBm of average output power, respectively, at −30 dB EVM for a commercial specification. In addition, the current combining PA is operated in a multi‐mode manner, which saves the power stage current about 225 mA of the power stage current at low power mode. No pre‐distortion technique is required and all components are integrated on the chip.

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“…With rapid development of wireless communications for the Internet of Things (IoT), RF integrated circuits (ICs) with compact chip size have become essential to reduce the unit cost of production . To realize compact chip area, a power amplifier should be designed using a CMOS process by which the analog and digital circuits are integrated .…”

Section: Introductionmentioning

confidence: 99%

A CMOS power amplifier using split input and output transformers to minimize its chip area

Jeong

Shin

et al. 2016

Microw. Opt. Technol. Lett.

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In this study, we propose a layout technique to reduce the chip area of differential RF CMOS power amplifiers in which input and output transformers are utilized as input and output baluns. To minimize the chip area of the CMOS power amplifier, we split a conventional spiral transformer into two identical parts, thereby making full use of the wasted area in the conventional power amplifier. Using the proposed split transformers in the input and output transformers, we successfully reduce the chip area of the CMOS power amplifier based on a differential structure. To verify the feasibility of the proposed split cascode structure, we designed a 2.4‐GHz CMOS power amplifier using a 180‐nm SOI RF CMOS process. With an IEEE 802.11n WLAN modulated signal, we obtain a maximum output power of 9.73 dBm. From the measured results, we verify the feasibility of the proposed split transformer structure for RF CMOS power amplifier applications. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1443–1446, 2016

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A Fully Integrated High Efficiency RF Power Amplifier for WLAN Application in 40 nm Standard CMOS Process

Cited by 24 publications

References 5 publications

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

A study comparing current and voltage combining techniques for CMOS power amplifiers for WLAN applications

A CMOS power amplifier using split input and output transformers to minimize its chip area

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