A fully integrated broadband direct-conversion receiver for DBS applications

Jayaraman, A.; Terry, B.; Fransis, B.; Sullivan, P. J. E.; Lindstrom, Mats; O’Connor, James T.

doi:10.1109/isscc.2000.839722

Cited by 37 publications

(16 citation statements)

References 2 publications

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“…Most existing direct broadcast satellite TV receivers (DBS) use a direct conversion architecture that does not have image channel rejection issues [1][2][3]. The 1/f noise contribution is less significant in bipolar implementations [1,2], while the DC offset in the baseband signal path was rejected either by using large off-chip coupling capacitors [1], or by implementing a DC offset cancellation loop [2,3].…”

Section: Introductionmentioning

confidence: 99%

“…The 1/f noise contribution is less significant in bipolar implementations [1,2], while the DC offset in the baseband signal path was rejected either by using large off-chip coupling capacitors [1], or by implementing a DC offset cancellation loop [2,3]. Realizing a single-chip DBS receiver requires the integration of a large digital core together with the sensitive analog front-end, mandating the use of CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

“…Another drawback of zero-IF tuners is their long settling time in the signal path after a step gain change, that does not allow a discrete-step AGC implementation. Zero-IF tuners usually use continuous AGC loops [1][2][3] that degrade the noise figure of the RF front-end and the linearity performance of the IF back-end.…”

Section: Introductionmentioning

confidence: 99%

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Notice of Violation of IEEE Publication Principles: A single-chip digitally enhanced radio receiver for DBS satellite TV applications

Maxim

Poorfard

Johnson

et al. 2008

2008 IEEE Radio and Wireless Symposium

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Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.Abstract -A digital low-IF receiver for satellite TV applications was realized in 110nm CMOS taking advantage of high speed and moderate resolution ADCs and high digital processing power available in nanometer CMOS. A discrete gain step signal path and a digital power level measurement together with a digital AGC loop implementation resulted in lower receiver area and power and a smaller noise figure penalty. Image rejection in excess of 50dB was achieved by using a continuous digital I/Q mismatch correction engine that relaxes the matching requirements on the analog front-end and thus reduces the occupied die area. A dynamic digital clock frequency management algorithm was implemented to avoid receiver de-sensitization due to digitally coupled in-band spurs. SoC specifications include: 0.2dB implementation loss, <1.3°rms integrated phase noise,<-50dBc spurs, <0.2s channel acquisition time, 1.2W power dissipation from a dual 1.8/3.3V supply and 1.8x4.8mm 2 die area.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Notice of Violation of IEEE Publication Principles: A single-chip digitally enhanced radio receiver for DBS satellite TV applications

Maxim

Poorfard

Johnson

et al. 2008

2008 IEEE Radio and Wireless Symposium

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“…After these considerations the final candidate is an oscillator bank: several VCOs with different frequency ranges are in parallel and one of these is active at any one time. Four [18] or as many as eight [20] parallel oscillators have been used. The number of VCOs has a severe impact on the total die area and therefore they should be kept to a minimum.…”

Section: Lo Generationmentioning

confidence: 99%

A Broadband Double-Conversion RF Tuner

Stadius¹,

Malinen²,

Jarvio³

et al. 2005

Analog Integr Circ Sig Process

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A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47-862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9-µm SiGe bipolar process.

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“…A wide tuning range VCO can be another choice to cover the dual bands [3], but the required wide tuning range varactors are not usually available in a standard process and the relatively large VCO gain ( ) can easily lead to severe phase noise degradation [4]. A set of multiple VCOs can support multiple bands [5], but this could be unaffordable in portable devices due to the overwhelming circuit overheads. In a particular dual-band application that requires a certain frequency ( ) and its double frequency , an emitter-coupled pair can be used to take the two frequencies from an output node and a common node, respectively [6], but such an integer multiplication or division is incapable of generating fractionally separated frequencies.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-v 6/9-GHz reconfigurable dual-band quadrature LC VCO in SiGe BiCMOS technology

Shin

Chang

2003

IEEE J. Solid-State Circuits

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This paper presents a dual-band voltage-controlled oscillator (VCO) that can be reconfigured between 6-and 9-GHz frequency bands. It comprises a 6-GHz LC-tuned VCO, two 1/2 dividers, two mixers, and two 3-GHz notch filters. The 9-GHz output is generated based on the analog frequency multiplication method by mixing the 6-GHz VCO output with its divide-by-two signal. The VCO, implemented in a 0.18-m SiGe BiCMOS technology, achieves a fast reconfiguration time of 3.6 ns. The measured VCO phase noises are 106 and 104 dBc/Hz at 1-MHz offset for 6-and 9-GHz modes, respectively, while draining 10.8 mA from a 1.8-V supply.Index Terms-Dual-band VCO, reconfigurable VCO, SiGe VCO, switchable VCO, voltage-controlled oscillator (VCO).

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A fully integrated broadband direct-conversion receiver for DBS applications

Cited by 37 publications

References 2 publications

Notice of Violation of IEEE Publication Principles: A single-chip digitally enhanced radio receiver for DBS satellite TV applications

Notice of Violation of IEEE Publication Principles: A single-chip digitally enhanced radio receiver for DBS satellite TV applications

A Broadband Double-Conversion RF Tuner

A 1.8-v 6/9-GHz reconfigurable dual-band quadrature LC VCO in SiGe BiCMOS technology

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