Most existing DBS tuners [1, 2, 3] use a direct-conversion architecture that requires a low frequency step in the synthesizer. This can be achieved either with a single-loop LC-oscillator-based PLL [1,2] or with cascaded PLLs [3]. A large number of LC oscillators are used in [1] to cover the wide satellite-TV spectrum, but drawbacks include large die area due to on-chip planar inductors and high sensitivity to magnetic noise coupling and frequency pulling. In [2], a size reduction is achieved by using only two LC oscillators and switching different capacitor banks to cover the wide frequency range; this comes at the price of degraded phase noise. A higher complexity dual-loop synthesizer is proposed in [3]. It uses an LC oscillator PLL to ensure fine frequency resolution, cascaded with a ring oscillator PLL to provide a wide frequency range. The stringent satellite-TV phase-noise specification (<2.8°r ms for QPSK and <2°r ms for 8-PSK modulation) requires a small loop-filter (LF) resistor, often leading to nF-range capacitors that are hard to integrate on-chip.In this paper, a single-loop fully integrated 0.13µm CMOS ring-oscillator-based frequency synthesizer for low-IF DBS receivers is presented. Figure 33.7.1 shows the top-level diagram of the single-chip DBS tuner-demodulator. The chip uses an analog mixing stage that downconverts a cluster of channels to a low IF (30 to 50MHz), followed by a second mixing stage implemented in the digital demodulator that performs the final channel selection. The low-IF tuner architecture does not increase circuit complexity since the second digital mixing is also required in the direct-conversion case to compensate for outdoor LNB oscillator temperature variations. A low-IF tuner can tolerate a wide frequency step from the synthesizer, allowing its implementation with a wideband ring-oscillator-based PLL. Using a ring oscillator reduces the synthesizer die size by a factor of 5 to 10 and provides lower sensitivity to magnetic coupling compared to that of existing LC-based solutions [1,2,3]. The challenges in this design are higher noise and spur contribution from the PLL front-end due to the required wide loop bandwidth and the large oscillator gain.The large tuning range and low supply voltage of deep-submicron CMOS lead to a very high oscillator gain (K vco ). Placing an attenuator (A t ) between the LF and the oscillator is equivalent to an oscillator gain reduction, which helps both front-end noise and spurs attenuation. For a given noise contribution from the LF, the attenuator allows the usage of a resistor A t 2 times larger and therefore reduces the size of the LF capacitance by A t 2 , enabling its on-chip integration. Figure 33.7.2 shows the noise-attenuating LF principle together with its circuit implementation. A passive-RC LF(C i , R, C p ) is used due to its excellent supply-noise rejection. The attenuator is realized with a resistor divider R d1 , R d2 , that needs to be buffered from the highimpedance node of the LF to avoid reference spurs degradation. To m...
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