A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage

Saito, Namiko; Tsukizawa, Takayuki; Shirakata, Naganori; Morita, Tadashi; Tanaka, Kōichiro; Sato, J.; Morishita, Yohei; Kobayashi, Masaki; Kitamura, Ryo; Shima, Takahiro; Nakatani, Toshifumi; Miyanaga, Kenji; Urushihara, Tomoya; Yoshikawa, Hiroyuki; Sakamoto, Takenori; Motozuka, Hiroyuki; Shirakawa, Yoshinori; Yosoku, Naoya; Yamamoto, Akira; Shiozaki, Ryosuke; Takinami, Koji

doi:10.1109/jssc.2013.2279573

Cited by 108 publications

(60 citation statements)

References 19 publications

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“…Since 75% of the power in ∆Σ DAC comes from the digital part, this DAC can benefit from further CMOS scaling which can further improve its FOM. An area comparison of this ∆Σ DAC with [70] and [58] is easier because these DACs are also designed in 65 nm CMOS. The ∆Σ DAC in this work has 1.6 times more area than the Nyquist DAC presented in [70].…”

Section: Measurement Resultsmentioning

confidence: 99%

“…An area comparison of this ∆Σ DAC with [70] and [58] is easier because these DACs are also designed in 65 nm CMOS. The ∆Σ DAC in this work has 1.6 times more area than the Nyquist DAC presented in [70]. In [58], although a very compact DAC is presented, a high performance analog transistor with 1.5 times better matching parameter, A vt is used.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…DACs that form a part of the transmitter baseband are hence required to have a wide bandwidth >880 MHz (in both, I & Q paths to enable the 1.76 GHz channel BW) and a resolution >6-8 bits to support the different modulation schemes of these standards [7,46,[70][71][72]. Most of the DACs reported in literature for 60-GHz radio have so far used a conventional approach with a 2× digital interpolation of the baseband, followed by a Nyquist current-steering DAC and a fourth or fifth order passive LC-analog anti-aliasing filter, which then connects to an up-conversion 76 A 11-GS/s 1.1-GHz BW TI-∆Σ DAC for 60-GHz Radio in 65-nm CMOS mixer [46,70].…”

Section: Introductionmentioning

confidence: 99%

“…Most of the DACs reported in literature for 60-GHz radio have so far used a conventional approach with a 2× digital interpolation of the baseband, followed by a Nyquist current-steering DAC and a fourth or fifth order passive LC-analog anti-aliasing filter, which then connects to an up-conversion 76 A 11-GS/s 1.1-GHz BW TI-∆Σ DAC for 60-GHz Radio in 65-nm CMOS mixer [46,70]. This approach is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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“…The authors have already developed a compact, low power consumption CMOS chipset targeted at mobile terminals such as smartphones [15]. The fabricated CMOS chipset employed various technologies, such as 1) Direct conversion architecture, 2) Frequency domain equalizer that compensates circuit frequency deviation and multipath fading, 3) Reduction of Fast Fourier Transform (FFT) size.…”

Section: Analog Beamforming For Phased Array Antennamentioning

confidence: 99%

Evolution of Millimeter-Wave Multi-Antenna Systems in the IoT Era

Takahashi

Yomo

Matsuoka

et al. 2017

IEICE Trans. Electron.

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SUMMARYIn this paper, we present the roles played by millimeterwaves in the realization of an Internet of Things (IoT) society. Millimeterwaves are becoming essential frequency resources, enabling ultra-highspeed wireless networks supporting massive data traffic and high-resolution sensor devices. Multiple antenna technologies such as phased arrays, sector antennas, and MIMO signal processing are key technologies for putting these into practical use. In this paper, various examples of integration of multi-antenna systems are shown, as well as demonstration on 60 GHzband millimeter-wave wireless access and 79 GHz-band high-resolution radar. We also propose applications to ITS for an IoT society, combining millimeter-wave wireless access and radar sensors, and discuss technical issues to be solved in the future.

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State-of-the-Art Millimeter-Wave Silicon Transceivers and Systems-on-Chip

Preez

Sinha

2022

Lecture Notes in Electrical Engineering

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A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage

Cited by 108 publications

References 19 publications

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Evolution of Millimeter-Wave Multi-Antenna Systems in the IoT Era

State-of-the-Art Millimeter-Wave Silicon Transceivers and Systems-on-Chip

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