2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) 2017
DOI: 10.1109/norchip.2017.8124993
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A fully integrated 13 GHz CMOS SOI stacked power amplifier for 5G wireless systems

Abstract: Abstract-This paper presents a fully integrated, four stack power amplifier for 5G wireless systems. The frequency of operation is tunable from 12 GHz to 14 GHz, with a maximum 3 dB bandwidth of 1 GHz and a maximum possible gain of 35 dB. The circuit is designed and fabricated using 45 nm CMOS SOI technology. Maximum RF output power, power-added efficiency (PAE) and output 1 dB compression point under maximum bandwidth configuration are 17.7 dBm, 23.2 % and 12.3 dBm, respectively, achieved at 13.7 GHz.

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Cited by 6 publications
(5 citation statements)
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“…The setup simulated in Matlab consist of memoryless lookup table (LUT) PA model, based on extracted simulation data of a 45nm 4-stack complementary metal oxide semiconductor (CMOS) silicon on insulator (SOI) PA [10]. Input waveform is 64-QAM signal with root-raised-cosine pulse shaping filter (roll-off factor of 0.35), bandwidth of 100 MHz and frequency of operation is 28 GHz.…”
Section: Array Dpd Setup Under Random Amplitude and Phase Variatmentioning
confidence: 99%
“…The setup simulated in Matlab consist of memoryless lookup table (LUT) PA model, based on extracted simulation data of a 45nm 4-stack complementary metal oxide semiconductor (CMOS) silicon on insulator (SOI) PA [10]. Input waveform is 64-QAM signal with root-raised-cosine pulse shaping filter (roll-off factor of 0.35), bandwidth of 100 MHz and frequency of operation is 28 GHz.…”
Section: Array Dpd Setup Under Random Amplitude and Phase Variatmentioning
confidence: 99%
“…The array has M A parallel antennas and PAs. In the simulations, we use a memoryless look-up table (LUT) PA model extracted from amplitude to amplitude modulation (AMAM) and amplitude to phase modulation (AMPM) measurements of a 13 GHz, 45-nm, 4-stack complementary metal oxide semiconductor (CMOS) silicon on insulator (SOI) PA [14]. The PA simulation model is presented in Fig.…”
Section: Statistical Dpd Architecture For Phased Array a Overviementioning
confidence: 99%
“…The transitions between the frequency and time domain models are calculated by using Discrete Fourier Transform (DFT). The PA model is a lookup table which is based on the AMAM & AMPM measurements of the 13 GHz 4-stack 45nm CMOS SOI PA [11]. The input waveform is 100 MHz The analysis is divided into three parts.…”
Section: A Pa Array Model and Simulation Parametersmentioning
confidence: 99%