A Fully FPGA Implementation of SVPWM for Three-phase Inverters without External Reference Signals

Donisi, Andrea; Benedetto, Luigi Di; Licciardo, Gian Domenico; Rubino, Alfredo; Piccirilli, Eduardo; Lanzotti, Emilio

doi:10.1109/eeeic/icpseurope49358.2020.9160724

Cited by 6 publications

(5 citation statements)

References 17 publications

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“…In order to show the generality of our HW architecture, we also implemented it in a low performance FPGA like Xilinx Artix 7 [34] whose 4.75% and 0.75% of LUT and FF are used. Indeed, although our system needs more resources than other like [25] even to the +2.35 and +1.27 times the required LUT and FF, respectively, or like [17] even to the +1.21 and +1.66 times the required LUT and FF, respectively, the possibility of setting several configurations of the output three-phase voltages in real-time justifies such increase. Moreover, the executive time results equal to three system clock periods and it is due to the presence of FFs between the combinational blocks of the system for the data consistency.…”

Section: Fpga Implementationmentioning

confidence: 98%

“…Such approach is unwanted when one needs a stand alone or an independent controller. On the other hand, other solutions use an internal memory [25] where the values of the dwell-times are stored for a fixed f C and f SW , but without the possibility to vary them in real-time. We overcome such limits and, although it is based on the approach to store the dwell-times in an internal memory of the controller, our HW architecture satisfies the following points:…”

Section: Theory Of the Proposed Hw Architecturementioning

confidence: 99%

“…We show our proposal by using FPGA digital controller integrated in a power AC/DC converter for asynchronous motor driving, but it can be also adapted for micro-controllers. The novelties introduced in this paper compared to others solutions [25], [26], that are based on the storage of precalculated dwell-times are as follows:…”

Section: Introductionmentioning

confidence: 99%

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Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

et al. 2022

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A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed. Its features are the reduced hardware resources and the real-time variation of the values of the carrier and switching frequencies, of the phase and of the amplitude of the three-phase output voltages in addition to not require external reference signals or further processors, like Digital Signal Processor. The basic idea is to pre-calculate a set of normalized dwell-time for only one sixth of the α − β-plane and, then, to reconstruct through our architecture the effective dwell-times and the right inverter configurations by an optimized management of the memory. The architecture is implemented in a Field Programmable Gate Array Cyclone V using the 6% and the 1.01%, respectively, of the Look-Up Tables and of the Flip Flops and the experimental measurements show the goodness of the generated waveforms and the high numbers of degrees of freedom without the demand of Digital Signal Processor or Personal Computer.INDEX TERMS Digital controller, field programmable gate array, space vector pulse width modulation, three-phase DC/AC power converter.

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Section: Fpga Implementationmentioning

confidence: 98%

Section: Theory Of the Proposed Hw Architecturementioning

confidence: 99%

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Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

et al. 2022

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“…However, there are several effort to implement SVPWM technique in FPGA controllers in order to simplify and to reduce the complexity of the algorithm, and there are solutions based on CORDIC algorithms [19] or on Look-Up table approaches [20], [21] and that can use DSPs [22] or external flash memory with an external signal reference [23]. However, there are some drawbacks: firstly, in the case of the external PCs or DSPs, one needs powerful hardware that limits the fields of applications, like stand-alone applications because SVPMW signal generator requires external reference signals; secondly, although hardware architectures based on LUT reduce the complexity and do not require external resources, the variations of the three-phase output waveform are only possible for multiple values of the reference value [20], [21], [24]. Moreover, FPGA manufactures provide FPGA core Intellectual Property modules to implement SVPWM technique, but they cannot be modified in order to optimize the resource for a specific applications as well as to improve the algorithm.…”

Section: Introductionmentioning

confidence: 99%

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

Di Benedetto,

Donisi,

Liguori

et al. 2024

IEEE J. Emerg. Sel. Topics Power Electron.

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A novel hardware digital architecture for the Space Vector Pulse Width Modulation technique is proposed and based on a novel algorithm for the evaluation of the dwell-times. Indeed, the complexity of the calculation of trigonometric functions is solved introducing a Taylor series decomposition and using a convenient definition of the space vector α − β plane. Our architecture can modify the dwell-times as function of the carrier and switching frequencies, of the phase and of the modulation index. Comparing to other techniques, it avoids the use of external reference voltages as well as of the pre-calculated dwelltimes, like for the LUT-based architectures. Although it can be implemented in several logic devices, an Altera Cyclone V Field Programmable Gate Array is used as a digital controller of a three-phase power inverters and its resources are the 16% and 2%, respectively, of the Look-Up Tables and of the Flip Flops. Several cases are studied in order to show the goodness of the output waveforms during the real-time variations of the inputs.

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“…It means that the proposals of the state-of-art need further hardware or software tools increasing the cost, the space and the complexity of the power system; differently, ours overcomes such limitations. Finally, compared with [10], in this paper we propose a procedure to optimize the resource of the controller in terms of the minimum LUT size and length of its cells as well as the possibility to change the switching frequency in real-time.…”

Section: Introductionmentioning

confidence: 99%

Design of Digital Controller for SVPWM Algorithm with Real-Time Control of the Output Amplitude and Switching Frequency

Donisi

Benedetto

Licciardo

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A new hardware design of digital system focused to Space Vector Pulse Width Modulation technique is shown. The system performs the real-time control of the output voltage amplitude and of the switching frequency as well as the delay between the three phase output voltages in order to change the direction of rotation of an asynchronous motor. Although the design can be applied to digital control devices, we focused to Field Programmable Gate Array and both architecture and experimental results are shown. The idea is to pre-calculate the dwell-times, which are normalized to the maximum amplitude modulation index, and to relate them at the corresponding switching configurations of the inverter. They are stored in the internal Look-Up Tables and all the operations are performed without any external devices or any external reference signals. A three-phase power inverter prototype supplies a 380VAC − 50Hz − 750W asynchronous motor with on-board Altera Cyclone V FPGA. Our architecture demands 243 FFs and 324 LUTs, which are the 0.66% and 1.75% of the overall system, respectively, avoids internal DSPs and has a low dynamic power dissipation of 0.54mW at a system clock frequency of 100M Hz. Our proposal interests those applications where the FPGA manages the overall power system and limited resources are required.

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A Fully FPGA Implementation of SVPWM for Three-phase Inverters without External Reference Signals

Cited by 6 publications

References 17 publications

Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

Implementation of Hardware Architecture for SVPWM With Arbitrary Parameters

A New Hardware Architecture for SVPWM Technique Based on the Taylor Decomposition

Design of Digital Controller for SVPWM Algorithm with Real-Time Control of the Output Amplitude and Switching Frequency

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