A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

Cheng, Shanfeng; Tang, Haitao; Silva-Martí­nez, J.; Karsilayan, A.I.

doi:10.1109/jssc.2006.891448

Cited by 49 publications

(18 citation statements)

References 7 publications

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“…The FoM (figure of merit) in most applications is valued with the ratio of maximum working frequency and power. It can be concluded that the FoM of proposed prescaler is much better than the static prescaler with reduced latch transistors' size in [17], almost better but not much worse than the dynamic load prescalers in [10,13], though it is less attractive than the injection-locked frequency prescalers in [19,20].…”

Section: Measurement Resultsmentioning

confidence: 99%

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Optimization and design of a novel prescaler and its application to GPS receivers

2011

Sci. China Inf. Sci.

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In this work, a novel prescaler based upon new current mode logic (CML) flip-flop architecture applied to global positioning system (GPS) receivers is proposed. Compared to traditional static current mode logic (CML) flip-flop, it introduces a clock-controlling transistor to reduce the time constant at sensing period. As a result, the speed has been maximized and the working range has been enlarged. The phase noise of local oscillator (LO) signals coming from the prescaler can be lowered by 6 dB, and the interference of voltage controlled oscillator (VCO) to radio-frequency (RF) front-end apartments (low noise amplifier, mixer, etc.) will be diminished so that the sensitivity of GPS receivers is enhanced. This prescaler's maximum input frequency rises up to 6.9 GHz, 30% higher than that of traditional architecture, and its power is only 2.16 mW when the supply voltage is 1.8 V. The prescaler was manufactured in 0.18-µm CMOS process, and it has been successfully applied to GPS receivers.

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Section: Measurement Resultsmentioning

confidence: 99%

“…Figure 9 IF output power spectrum. Wang [11] Razavi [13] Liu [17] Kim [18] Cheng [19] Tsai [20] Proc. …”

Section: Figurementioning

confidence: 99%

Optimization and design of a novel prescaler and its application to GPS receivers

2011

Sci. China Inf. Sci.

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“…Frequency dividers can be classified into three categories according to the cell: (1) The CML latch [3,8,26], which has a good stability and low noise, but the current consumption is often large, so it's suitable for low-noise applications; (2) the True Single Phase Clock (TSPC) latch [17], whose structure is so simple that the small amount of internal nodes ensures little parasitic, so it can operate under a high frequency with low power consumption; (3) the Injection Locked Frequency Divider (ILFD) cell [4,9,13,29,31], which is usually used under a very high frequency.…”

Section: The Proposed I/q Lo Signal Generatormentioning

confidence: 99%

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

Zhao

Guo

Yang

et al. 2011

Analog Integr Circ Sig Process

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A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430-435 MHz PLL for frequency synthesizing, a 1.72-1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are -19.9 and -20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are -61.2 dBc@20 MHz and -57.7 dBc@40 MHz at the output of the PLL, and -70.5 dBc@20 MHz and -66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.

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“…TUNING MECHANISM OF RILFD Generally, ILFDs have been designed with two kinds of VCOs such as an LC-type [3][4][5][6][7][8][9] and a ring-type oscillator [10][11][12][13][14][15][16][17]. To inject an input signal to the oscillator, direct and tail injection methods are used.…”

Section: Operating Speed Improvement and Frequencymentioning

confidence: 99%

A 110GHz inductor-less CMOS frequency divider

Lim

Badalawa

Fujishima

2009

2009 IEEE Asian Solid-State Circuits Conference

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An inductor-less 110GHz ring-type frequency divider (RILFD) has been proposed. Body-injection and biasing technique have been adopted to achieve high speed and divideby-three operation and fine tuning of operation frequency. The RILFD was fabricated by a 1P12M 65nm bulk CMOS process. The core size is 10.8×8.5μm2. The locking range is 9.1%, from 100.8 to 110.4GHz, under varying of body-bias voltage from -0.2V to 0.4V. The RILFD consumes 4.5mW at the supply voltage of 1V excluding an output buffer. The output phase noise is -117.6dBc/Hz at 1MHz offset. This work has been achieved the smallest core size among frequency dividers reported to date operating over 100GHz.

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A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

Cited by 49 publications

References 7 publications

Optimization and design of a novel prescaler and its application to GPS receivers

Optimization and design of a novel prescaler and its application to GPS receivers

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

A 110GHz inductor-less CMOS frequency divider

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