A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

Upadhyaya, Parag; Poon, Chi Fung; Lim, Siok Wei; Cho, Junho; Roldan, Arianne; Zhang, Wenfeng; Namkoong, Jin; Pham, Thanh-Hang; Xu, Bruce; Lin, Winson; Zhang, Hongtao; Narang, Nakul; Tan, Kee Hian; Zhang, Geoff G. Z.; Frans, Yohan; Chang, Ken

doi:10.1109/jssc.2018.2875091

Cited by 28 publications

(7 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, the encoder block in front of the output driver can be removed, decreasing the data path delay and improving the output drift characteristic. Although the differential PAM-4 transmitter [8,11] has better energy efficiency, the differential architecture with the on-chip voltage regulator cannot be adopted in memory interfaces. The previous single-ended PAM-4 transmitter [13] has better RLM and energy efficiency performances; however, the impedance values of the NMOS-only driver are vulnerable to the VT variations, and the circuits for the ZQ calibration are needed, even in the main path.…”

Section: Conflicts Of Interestmentioning

confidence: 99%

“…However, a PAM-4 signal has only one third of the eye height of an NRZ signal, resulting in a signal-to-noise ratio (SNR) attenuation by 9.5 dB [6,7]. In addition, further SNR degradation may occur due to the non-linearity characteristics of the transmitter output [8]; this causes an imbalance between PAM-4 signal levels. Since the overall performance depends on the smallest eye height of the transmitter, it is important to equalize the voltage difference between signal levels [8] while matching the channel impedance at each signal level.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

View full text Add to dashboard Cite

This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.

show abstract

Section: Conflicts Of Interestmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

View full text Add to dashboard Cite

show abstract

“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

Section: Cmos Inverter As An Amplifiermentioning

confidence: 99%

“…The last example is the output driver for high-speed I/O link. On the right side of Figure 12, we can find a conceptual diagram of a source-series terminated (SST) driver, which is also known as a voltage-mode driver [35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50]. Instead of relying on a parallel resistance to match the driver's output impedance with the characteristic impedance of the transmission channel, the SST driver adopts series termination.…”

Section: Output Driver For High-speed Wireline Communicationmentioning

confidence: 99%

CMOS Inverter as Analog Circuit: An Overview

Bae

2019

JLPEA

View full text Add to dashboard Cite

Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

show abstract

“…Ultra-high sample rate analog-to-digital converters (ADCs) operating at several tens of gigahertz are increasingly demanded in leading-edge instruments, optical communications, multiple-input multiple-output (MIMO) systems, and 6G communications [1][2][3][4][5][6]. Benefiting from the technology scale and digital architecture, successive approximation register (SAR) ADC shows prominent advantages in power efficiency and area occupation for high-speed and moderate-resolution designs.…”

Section: Introductionmentioning

confidence: 99%

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

Luan

Zheng

et al. 2022

Electronics

View full text Add to dashboard Cite

This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm2 and consumes 432 mW power consumption.

show abstract

A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET

Cited by 28 publications

References 9 publications

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

CMOS Inverter as Analog Circuit: An Overview

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

Contact Info

Product

Resources

About