A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling

Pandey, Parul; Vishnoi, Rajat; Kumar, M. Jagadesh

doi:10.1007/s10825-014-0649-x

Cited by 36 publications

(13 citation statements)

References 28 publications

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“…where A 1 , A 2 , B 1 , and B 2 are deduced using the boundary conditions (8)(9)(10)(11)(12) as shown below in (33).…”

Section: Partial Depletion (Gate1) and Near Flatband (Gate2)mentioning

confidence: 99%

“…Instead, the electrostatic performance of the device can be significantly improved by incorporating a step in the surface potential profile using a Dual Material Gate (DMG). The DMG concept has been widely studied to demonstrate the simultaneous suppression of the SCEs and enhancement of trans-conductance, due to the introduction of a step function in the channel surface potential [2][3][4][5][6][7][8][9][10][11]. Recently, improvements in electrical characteristics have been demonstrated by using the DMG structure in planar JLFETs and junctionless nanowire transistors [12,13].…”

Section: Introductionmentioning

confidence: 99%

“…Most of the models developed for DG JLFET did not account for depletion into the source and drain regions. In this paper, the depletion regions extending into source (d S ) and drain (d D ) are also considered [10,17]. …”

Section: Introductionmentioning

confidence: 99%

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A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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In this paper, we have developed a pseudo twodimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

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“…where A 1 , A 2 , B 1 , and B 2 are deduced using the boundary conditions (8)(9)(10)(11)(12) as shown below in (33).…”

Section: Partial Depletion (Gate1) and Near Flatband (Gate2)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

2015

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“…On the other hand, an increase in on-current causes the RF performances of the TFETs to be enhanced. To enhance the TFET on-currents, many efforts have been made including hetero-structures 11,16,17 , bandgap engineering 18,20 , high mobility and low band-gap materials 20,23 , high-k dielectric materials 24,25 , heterogate-dielectric (HG) 26,27 , dual material gate 28,30 and vertical direction tunneling 31,32 .…”

Section: Introductionmentioning

confidence: 99%

Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

Marjani¹,

Khosroabadi²,

Hosseini³

2017

Orient. J. Chem

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In this paper, for the first time, the square-shaped extended source tunneling field-effect transistor (SES TFET) by means of the silicon carbide polytype (3C-SiC) and dopant pocket layer has been presented. By inserting the silicon carbide polytype as substrate and n-type pocket in the channel at the source edge, on-current is increased by about 10 times compared with the conventional SES TFET because of the reduced losses and energy band modification imposed by the silicon carbide and pocket doping, respectively. Additionally, using calibrated simulations, the SES TFET with 3C-SiC substrate and dopant pocket layer is evaluated in terms of various radiofrequency (RF) parameters, including the gate to source capacitance, gate to drain capacitance, trans conductance, channel resistance, transport time delay, cutoff and maximum oscillation frequencies. The simulation results of the SES TFET with the 3C-SiC substrate and dopant pocket layer exhibits a superior switching-state current ratio ( ̴ ̴ 10 13 ) and a small transport time delay (about 0.15 psec) that is a hopeful candidate for conventional SES TFET.

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“…Tunneling field-effect transistors (TFETs) are now attracting much interest as an alternative to transistor design for future ultralow voltage domain because of their low off-state leakage current (I of f ) and low subthreshold slope (SS). Since the current is controlled by the band-to-band tunneling (BTBT) mechanism on the sourcechannel interface, TFETs can achieve the subthreshold slope of less than 60 mV/decade at room temperature, which allows for a more aggressive reduction of the threshold and supply voltages [1][2][3][4][5][6][7]. However, planar silicon-based TFETs have very low on-state currents (I on ) compared to conventional MOSFETs (typically three to five decades) because of poor band-to-band tunneling efficiency, which is a serious drawback in circuit applications.…”

Section: Introductionmentioning

confidence: 99%

A 3D analytical modeling of tri-gate tunneling field-effect transistors

2016

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In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the trigate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson's equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.

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A full-range dual material gate tunnel field effect transistor drain current model considering both source and drain depletion region band-to-band tunneling

Cited by 36 publications

References 28 publications

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

A 3D analytical modeling of tri-gate tunneling field-effect transistors

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