A full functional Monolithic Active Pixel Sensor prototype for the CEPC vertex detector

Wu, Tianya; Lu, Weiguo; Dong, J.; Li, Long; Wang, J.; Zheng, Ran; Yang, P.; Grinstein, S.; Casanova, R.; Wei, Wei; Wei, Xiaomin; Zhang, Ying; Zhang, Liang; Li, Xiaoting; Liang, Z.; Costa, J. Guimarães da

doi:10.1109/icecs46596.2019.8965105

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…In the primary design, the readout time of a pixel address is 50 ns for the pixel array of 512 × 1024. Since a pixel pitch less than 25 µm is expected, the pixel design only keeps the key parts in ALPIDE and FEI3, and the pixel details can be found in [7]. In order to satisfy the dead time, all the 512 DCOLs in the pixel array are parallel read out.…”

Section: Design Overviewmentioning

confidence: 99%

High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

Wei¹,

Wei²,

Wu³

et al. 2019

J. Inst.

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A: CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. The characteristics of the sensing diode and the readout architecture were studied using several chips with small-scaled pixel array for CEPC vertex detector. This paper will study the design of a high data-rate readout logic design of a 512 × 1024 pixel array. For the innermost layer of CEPC vertex detector, the hit pixel frequency is near 120 MHz, which is several times higher than the design requirements of ALPIDE for ALICE vertex detector. Based on the hit-driven readout scheme in the pixel array of ALPIDE and FEI3, we propose a new peripheral readout logic design. All the double columns of pixels are read out in parallel and a fast readout architecrue of 512 double columns is realized. Meanwhile, a real-time data compression and a trigger-mode operation are supported to reduce the data output. The simulation results indicate the pixel hit frequency in 1Corrrsponding author.

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Section: Design Overviewmentioning

confidence: 99%

High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

Wei¹,

Wei²,

Wu³

et al. 2019

J. Inst.

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show abstract

“…It has been implemented in a 0.18 µm CMOS Image Sensor (CIS) process. It includes a 192 × 64 matrix with a pixel size of 25 × 25 µm 2 [4]. Regarding the previous pixel sensor prototypes for the CEPC vertex detector, the TaichuPix1 is the first to satisfy both pixel size and readout speed.…”

Section: Jinst 16 P09020mentioning

confidence: 99%

“…the same peripheral readout logic was implemented at the end of the column. More details about the readout architecture can be found in [4].…”

Section: Jinst 16 P09020mentioning

confidence: 99%

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

Wu¹,

Grinstein²,

Casanova³

et al. 2021

J. Inst.

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Mechanical design of an ultra-light vertex detector prototype for CEPC

Liang

Zeng

et al. 2022

Radiat Detect Technol Methods

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A full functional Monolithic Active Pixel Sensor prototype for the CEPC vertex detector

Cited by 4 publications

References 14 publications

High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

Mechanical design of an ultra-light vertex detector prototype for CEPC

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