A frequency modulated PLL for EMI reduction in embedded application

Michel, J.; Neron, C.

doi:10.1109/asic.1999.806535

Cited by 33 publications

(11 citation statements)

References 2 publications

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“…One is to control the variation of the divider and the other is to modulate the VCO directly. In the former case a fractional-N PLL with a ΣΔ modulator is mostly used [1]- [7]. It has the advantage of being fully digital controlled.…”

Section: Introductionmentioning

confidence: 99%

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A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation

Hsieh

Kao

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSG has been fabricated in a 0.35um CMOS process. The clock of 400MHz with center spread ratios of 1.25% and 2.5% are verified. The size of chip area is 0.90×0.89mm 2 .

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Section: Introductionmentioning

confidence: 99%

“…Spread-spectrum clock generators (SSCG) have been widely employed as high-speed sources with reduced EMI levels [1]- [7]. Basically, SSCG is a phase locked loop (PLL) with special case of frequency modulation.…”

Section: Introductionmentioning

confidence: 99%

A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation

Hsieh

Kao

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Introduction: A phase-locked loop (PLL) with an appropriate frequency modulated output is usually used to generate a spread spectrum clock generator (SSCG) in many conventional approaches [1][2][3][4][5]. Usually, there are three kinds of modulation schemes employed in a PLL, among which direct modulation of the voltage-controlled oscillator (VCO) in a PLL [3][4][5] has been widely used owing to its simple architecture and absence of sigma-delta modulator noise.…”

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confidence: 99%

Digitised spread spectrum clock generator using direct variable current modulation

Guo

Zhang

2010

Electron. Lett.

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A fully-integrated digitised spread spectrum clock generator (D-SSCG) using direct variable current modulation is presented. The proposed D-SSCG realises the spread spectrum function by only adding some micro-current source branches into a conventional clock generator. It has been fabricated in a 0.5 mm BCD process and applied to a flyback converter, among which the D-SSCG consumes 1.68 mW and occupies an area of 0.032 mm 2 . Compared with other SSCGs, the proposed D-SSCG is simpler, and has advantages such as good robustness, small size, and low power consumption.

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“…This stringent settling time requirement is far shorter than that of a conventional SSCG. Figure 3 shows a block diagram of a conventional SSCG based on a fractional PLL [3,4,6,[10][11][12][13][14][15][16][17][18][19][20]. It consists of a phase frequency detector (PFD), a charge pump (CP), a 3rd order loop filter (LF), a voltage controlled oscillator (VCO), a multimodulus divider (MMD), a programmable counter (PGC), a ΣΔ modulator (ΣΔ), and a wave generator (WG).…”

Section: Introductionmentioning

confidence: 99%

“…The serialto-parallel converter (S/P) converts from the DATA to the received parallel data (RD) by using the CLK. In this SATA-PHY, the SSCG is applied a fractional SSCG because of a large EMI reduction [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The fractional SSCG should be narrow loop bandwidth because the quantized noise originated from a ΣΔ modulator is removed.…”

Section: Introductionmentioning

confidence: 99%

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

Kimura

Suzuki

Noto

2015

Journal of Electrical and Computer Engineering

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A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 s to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 m CMOS and achieves settling time of 3.91 s faster than 8.11 s of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 m and 18 mW, respectively.

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A frequency modulated PLL for EMI reduction in embedded application

Cited by 33 publications

References 2 publications

A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation

A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation

Digitised spread spectrum clock generator using direct variable current modulation

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

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