A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems

Abstract

Mixed-time critical systems are real-time systems that accommodate both hard real-time (HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase latency, while SRT tasks have average-case bandwidth (BW) demands. Memory requests in mixed-time critical systems usually have different transaction sizes based on whether the issuer task is HRT or SRT. For example, HRT tasks often issue requests with a cache line size. On the other side, SRT tasks may issue requests with a size of KBs. Requests from multimedia cores, cores controlling network interfaces and direct memory accesses (DMAs) are obvious examples of these large-size requests. Based on these observations, we promote in this work a new approach to schedule memory requests. This approach retains locality within large-size requests to minimize the worst-case latency, while maintaining the average-case BW as high as required. To achieve this target, we introduce a novel and compact time-division-multiplexing scheduler that is adequate for mixed-time critical systems. We also present a novel framework that constructs optimal offchip DRAM memory controller schedules for multi-core mixedtime critical systems. These schedules are loaded to the memory controller during boot-time. Based on the proposed schedule, we provide a detailed static analysis that guarantees predictability. We compare the proposed controller against state-of-the-art realtime memory controllers using synthetic experiments as well as a practical use-case from multimedia systems. 307 978-1-4799-8603-3/15/$31.00 ©2015 IEEE

Predictable Cache Coherence for Multi-core Real-Time Systems

“…These tasks can belong to a parallel application that is distributed across cores, or different applications that communicate between each other. Cores can share the whole shared memory space similar to [21] or share part of the memory space similar to [23]. We do not impose any restrictions on how the interference on the shared memory is resolved, whether it is the LLC or the DRAM.…”

“…TDM can be either time-conserving or non time-conserving. Time-conserving TDM grants the slot to the next core if the current core does not have pending requests, while in non-time conserving TDM such slot remains idle [21]. We use a TDM slot width that allows for one data transfer between shared memory and the private cache including the overhead of necessary coherence messages.…”

“…RELATED WORK Recent research efforts investigated the access latency overhead resulting from shared buses [2], [15], caches [16]- [18], and dynamic random access memories (DRAMs) [19]- [21]. For shared caches, most of these efforts primarily focused on preventing a task's data accesses from affecting another task's data accesses.…”

“…For example, the number of cores in the system has to be less than or equal to the number of DRAM banks to be able to achieve isolation at DRAM. Recent works [21]- [23] recognized these limitations, and offered solutions for sharing data. Authors in [21] share the whole memory space between tasks for main memory, and [22], [23] suggested a compromise by dividing the memory space into private and shared segments for caches.…”

“…Recent works [21]- [23] recognized these limitations, and offered solutions for sharing data. Authors in [21] share the whole memory space between tasks for main memory, and [22], [23] suggested a compromise by dividing the memory space into private and shared segments for caches. Nonetheless, these approaches focus on the impact of sharing memory on timing analysis, and they do not address the problem of data correctness resulting from sharing memory.…”