A Framework for Customizable FPGA-based Image Registration Accelerators

Abstract

Image Registration is a highly compute-intensive optimization procedure that determines the geometric transformation to align a floating image to a reference one. Generally, the registration targets are images taken from different time instances, acquisition angles, and/or sensor types. Several methodologies are employed in the literature to address the limiting factors of this class of algorithms, among which hardware accelerators seem the most promising solution to boost performance. However, most hardware implementations are either closed-source or tailored to a specific context, limiting their application to different fields. For these reasons, we propose an open-source hardware-software framework to generate a configurable architecture for the most compute-intensive part of registration algorithms, namely the similarity metric computation. This metric is the Mutual Information, a well-known calculus from the Information Theory, used in several optimization procedures. Through different design parameters configurations, we explore several design choices of our highly-customizable architecture and validate it on multiple FPGAs. We evaluated various architectures against an optimized Matlab implementation on an Intel Xeon Gold, reaching a speedup up to 2.86×, and remarkable performance and power efficiency against other state-of-the-art approaches. CCS CONCEPTS• Hardware → Hardware accelerators; • Computer systems organization → Reconfigurable computing; • Applied computing → Health informatics.

Dovado: An Open-Source Design Space Exploration Framework

“…As future works, we will improve the parser to define design space more broadly in terms of code transformations [16] and parameter optimization for a further boost. We plan to support newer languages, such as Chisel [2] or SpinalHDL [3], that offer a convenient way for highly parametrizable hardware or to support high-level synthesis approaches for fast architecture choices explorations [35]. Currently, Dovado lacks in run-time performance modeling of RTL modules.…”

Faber: A Hardware/SoftWare Toolchain for Image Registration

“…In this configuration, the most employed metrics are cross-correlation, mean square error, and mutual information [1] or its normalized version with nonparametric Parzen windows [14]. As for the optimization [6] Open Full Toolchain SimpleElastix [17] Open Full Toolchain HW GPU [21] Open Full Single Configuration GPU [22] Open Full Single Configuration GPU [24] Open Full Single Configuration GPU [23] Open Full Single Configuration FPGA [7] Closed Full Single Configuration FPGA [19] Closed Full Single Configuration FPGA [27] Closed Full Single Configuration FPGA [10] Open Full Single Configuration Faber (this work) Open Partial Toolchain algorithms, evolutionary strategies [15] and Powell's method [16] are among the most used ones [1]. These components properly combined generate a registration pipeline that can be tailored to various applications.…”

“…Nevertheless, it requires programming knowledge and a deep understanding of the algorithm to tune the hyperparameters. On the other hand, hardware (HW) accelerators are gaining traction as an alternative for higher performance and energy efficiency with two main approaches: GPUbased and FPGA-based [3], [7], [8], [9], [10], [11], [12]. The former is a valuable solution when images, particularly volumes, are involved, but it lacks energy efficiency.…”

“…To overcome the current literature limitations and bridge the gap between the flexibility of SW libraries and the benefits of accelerated HW approaches, we extend our previous work focused on a single similarity metric (i.e., MI) [10], and propose Faber. To the best of the authors' knowledge, Faber is the first open-source 1 HW/SW toolchain tailored to IR, offering optimized and highly customizable FPGA-based accelerators.…”

Hardware Architectures for Real-Time Medical Imaging

“…FPGAs have been designed to perform image registration of medical images as well. Specific processes as affine transformations or mutual information calculations can be accelerated during real-time image registration, implementing the algorithms in FPGAs [126,127]. Nevertheless, recently, Mondal and Banerjee proposed an efficient and complete hardware-based image registration [128].…”