A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

“…The noise of the current source is inversely proportional to its output current [5]. Using current sources also leaves little headroom at lower supply voltages.…”

“…10. However, flicker noise is not elaborated on in [5]. In the following section, we present a way to reduce the component count and replace the current sources with passive devices.…”

“…The sub-sampling PLL presented in [5] and shown in Fig. 1, uses a DTC in the reference path and a PI in the feedback path to align the phase of the voltage-controlled oscillator (VCO) with the phase of the reference clock, thereby enabling fractional-N operation.…”

“…They are used in a variety of applications, e.g., clock-and data recovery (CDR) circuits [1], [2], for phase acquisition in phase-locked loops (PLL) [3], [4], phase ramp generator in sub-sampling PLLs [5]. A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay.…”

“…A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay. Several PI topologies have been proposed; Delay line based [6], [7], trigonometric [2], [8], [9], current-weighting [1], [3], [4], [10], [11], charge-steering [12] and constant-slope charging [5], [13].…”