IEEE J. Solid-State Circuits
 2022
DOI: 10.1109/jssc.2022.3206955
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A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

Simone M. Dartizio
1
,
Francesco Buccoleri
2
,
Francesco Tesolin
3
et al.
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Cited by 10 publications
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References 26 publications
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A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS

Yang,
Xu,
Meng
et al. 2024
2024 IEEE Custom Integrated Circuits Conference (CICC)
0
0
0
0
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A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS

Yang,
Xu,
Meng
et al. 2024
2024 IEEE Custom Integrated Circuits Conference (CICC)
0
0
0
0
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4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology

Castoro
1
,
Dartizio
2
,
Tesolin
3
et al. 2023
2023 IEEE International Solid- State Circuits Conference (ISSCC)
9
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3
0
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4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Dartizio
1
,
Tesolin
2
,
Castoro
3
et al. 2023
2023 IEEE International Solid- State Circuits Conference (ISSCC)
11
0
2
0
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