4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

CMOS phase-locked loops in ISSCC 2023

“…In ISSCC 2023, it is becoming a significant trend that the performances improvements of the PLL, including the analog charge-pump based PLL (CPPLL) [1] , sub-sampling PLL(SS-PLL) [2] and all-digital PLL (ADPLL) [3−5] , rely more and more on the digital calibration algorithms. Based on the LMS algorithm with several dedicated circuits design, the fractional spur of low-jitter ADPLL can be reduced, the nonlinearity of the VCO in a PLL-based FMCW frequency synthesizer can be overcome to improve modulation bandwidth [1] , the quantization noise of the fractional-N PLL can be significantly reduced [2−5] , and the equivalent reference frequency of the PLL can be multiplied by more than 100 times to enable the adoptation of a 32-kHz low-frequency reference clock without significant performance degradation [4] .…”

“…Although ring VCO (RVCO) based PLL can easily achieves wide FTR with compact area and low power, its jitter is usually worse than the LC counterpart. Hence, to break this trade-off, a wideband frequency synthesizer, which consists of two cascaded PLLs, has been reported in ISSCC 2023 [2] . In such work, the first stage is a fractional-NLC-based SSPLL with narrow FTR to generate a GHz refer-ence clock for the second stage PLL with low-jitter and high frequency resolution, and the second stage is a ring PLL, which can easily cover wide frequency range with low power.…”