“…In ISSCC 2023, it is becoming a significant trend that the performances improvements of the PLL, including the analog charge-pump based PLL (CPPLL) [1] , sub-sampling PLL(SS-PLL) [2] and all-digital PLL (ADPLL) [3−5] , rely more and more on the digital calibration algorithms. Based on the LMS algorithm with several dedicated circuits design, the fractional spur of low-jitter ADPLL can be reduced, the nonlinearity of the VCO in a PLL-based FMCW frequency synthesizer can be overcome to improve modulation bandwidth [1] , the quantization noise of the fractional-N PLL can be significantly reduced [2−5] , and the equivalent reference frequency of the PLL can be multiplied by more than 100 times to enable the adoptation of a 32-kHz low-frequency reference clock without significant performance degradation [4] .…”