A FPGA Implementation of Hard Systematic Error Correcting codes based Matching of Data Encoded Architecture with Low-Complexity, Low-Latency

Shirol, Suhas B.; Ramakrishnan, S.; Kumar, Priyatam; Shetta, Rajashekar B

doi:10.1109/iceca.2018.8474614

Cited by 1 publication

(2 citation statements)

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Section: Introductionmentioning

confidence: 99%

“…To avoid transmission error, [15,16] provided a data error-correcting method to solve the problem. An error correcting code was realized on a Spartan 6 field-programmable gate array (FPGA) as a board with low complexity in [15]. A low-cost chip design includes a data detecting, correcting, encrypting and decrypting which was implemented using TSMC 0.18 µm process in [16].…”

Section: Introductionmentioning

confidence: 99%

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A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

et al. 2020

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In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.

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Section: Introductionmentioning

confidence: 99%