A FPGA-based implementation of a fault-tolerant neural architecture for photon identification

Abstract

Event identification in photon counting ICCD detectors requires a high level image analysis which cannot be easily described algorithmically: neural networks are promising to approach this application. A system capable of identifying these events on board of satellites needs fault tolerant capabilities to certify result correctness. The rapid evolution of the problem specification, due to the increasing knowledge about the physics, makes attractive the availability and modifiability of prototypes: FPGA-based design is effective to realize these systems. The paper presents therefore an FPGA-based implementation of a fault tolerant neural architecture for event identification.

An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing

“…FPGAs are suitable for prototypes of systems [2] whose correct operation is necessary for the evaluation of new architectures. This requires changing the architecture during the design cycle with many reconfigurations of the same FPGA.…”

Novel technique for testing FPGAs

“…that in [11]) whose correct operation is a critical factor for the evaluation and experimentation of new architectures. In these cases, it may be necessary to evolve the system functionalities according to experiment needs, or to reuse the same FPGAs in alternative solutions to be experimented on the field.…”

“…In these cases, it may be necessary to evolve the system functionalities according to experiment needs, or to reuse the same FPGAs in alternative solutions to be experimented on the field. This scenario is typical of several physic and space applications [12,11,13].…”

Experimenting genetic algorithms for training a neural network prototype for photon event identification

“…It consists of a high gain electron multiplier, based on MicroChannel Plates (MCP), a readout system based on a phosphor screen fibre-optically coupled to a fast-scanned CCD camera, and of a signal processing unit for event identification and centroiding, to localise events to sub-pixel accuracy. As far as the optical and CCD sub-systems are concerned, offthe-shelf devices were employed; for the processing system, an ad-hoc design of a neural unit was accomplished [1,2,6], whose implementation was realised by means of FPGA technology [18]. The whole detector system is currently being tested and debugged at our lab.…”