A Four-Step Incremental ADC Based on Double Extended Binary Counting With Capacitive DAC

Oh, Byungjoo; Kim, Jae Joon

doi:10.1109/tcsii.2019.2943171

Cited by 4 publications

(1 citation statement)

References 10 publications

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“…To meet these requirements, the integrated analog-todigital converter (ADC) plays a key role. In recent years, the extended counting (EC) ADC has been developed as an excellent candidate among various kinds of the ADC solutions for large-scale sensor array ROICs [14][15][16][17][18]. Compared with other ADC types such as successive approximate register (SAR) ADC, delta-sigma (Δ-Σ) ADC, and SS-ADC, EC-ADC achieves a good balance between bit-depth, conversion speed, and area.…”

Section: Introductionmentioning

confidence: 99%

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

Zhou

et al. 2022

Journal of Sensors

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As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

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Section: Introductionmentioning

confidence: 99%

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

Zhou

et al. 2022

Journal of Sensors

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Neckband-Based Continuous Blood Pressure Monitoring Device With Offset-Tolerant ROIC

et al. 2022

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This study presents a wearable neckband device for continuous cuffless blood pressure (BP) monitoring, where reliable neck-based BP measurement is achieved by utilizing the electrocardiogram (ECG) and impedance plethysmogram (IPG). Optimal composition and position of sensing electrodes around the neck were decided with consideration for physiological characteristics of the human body, and the core parameter of IPG magnitude was experimentally selected to improve the BP estimation accuracy. For its small-featured noises-tolerant detection capability, a customized readout integrated circuit (ROIC) was developed, which includes two kinds of analog front-ends (AFEs) for biopotential and bio-impedance. Both AFEs are proposed to include an attenuator-assisted hybrid DC-servo loop (DSL) structure, achieving precise pulse transit time (PTT) calculation by lowering the high-pass filtering cutoff frequency and also stable signal acquisition by widening the offset-cancellation range. Real-time PTT monitoring and BP estimation are wirelessly conducted, and its continuous operation time with 350-mAh battery capacity is longer than 5 hours. Efficacy of the proposed neckband BP device was evaluated for 8 healthy subjects under the physical stress condition, where the mean correlation coefficient and the standard deviation were achieved as 0.8508 and 4.17mmHg respectively.INDEX TERMS Neckband device, pulse transit time, continuous blood pressure monitoring, impedance plethysmogram, readout integrated circuit.

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A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

et al. 2022

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We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.INDEX TERMS Industrial applications, sensor interface, versatility, system-on-chip (SoC), system-inpackage (SiP), thermal management. Author et al.: Preparation of Papers for IEEE TRANSACTIONS and JOURNALS TABLE 1. Performance Comparison of High-Voltage and High-Power Class-D Power Amplifiers. YVES AUDET (Member, IEEE) received the B.Sc. degree and the M.Sc. degree in physics from the

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A Four-Step Incremental ADC Based on Double Extended Binary Counting With Capacitive DAC

Cited by 4 publications

References 10 publications

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

Neckband-Based Continuous Blood Pressure Monitoring Device With Offset-Tolerant ROIC

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

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